Simulation Results: spi_host

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.95 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 44.000s 1812.305us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 8.000s 22.059us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 8.000s 36.043us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 10.000s 190.021us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 10.000s 111.964us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 9.000s 49.335us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 8.000s 36.043us 5 5 100.00
spi_host_csr_aliasing 10.000s 111.964us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 5.000s 36.768us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 5.000s 45.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 6.000s 21.896us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 12.000s 783.040us 10 10 100.00
spi_host_error_cmd 8.000s 17.967us 10 10 100.00
spi_host_event 43.000s 7024.328us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 4.000s 62.681us 10 10 100.00
speed 10 10 100.00
spi_host_speed 4.000s 62.681us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 4.000s 62.681us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 611.000s 144199.101us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 26.000s 859.456us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 5.000s 159.429us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 4.000s 62.681us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 4.000s 62.681us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 44.000s 1812.305us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 44.000s 1812.305us 10 10 100.00
stress_all 9 10 90.00
spi_host_stress_all 47.000s 8836.573us 9 10 90.00
spien 10 10 100.00
spi_host_spien 166.000s 26519.770us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 863.000s 339550.389us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 7.000s 336.675us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 12.000s 783.040us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 9.000s 20.009us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 6.000s 32.649us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 7.000s 28.104us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 7.000s 28.104us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 8.000s 22.059us 1 1 100.00
spi_host_csr_rw 8.000s 36.043us 5 5 100.00
spi_host_csr_aliasing 10.000s 111.964us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 78.523us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 8.000s 22.059us 1 1 100.00
spi_host_csr_rw 8.000s 36.043us 5 5 100.00
spi_host_csr_aliasing 10.000s 111.964us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 78.523us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 115.350us 25 25 100.00
spi_host_sec_cm 4.000s 231.823us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 115.350us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_stress_all 32078792994332251789381004602528731466244981477316069390070082477120907369644 232
UVM_INFO @ 10080602333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---