Simulation Results: sram_ctrl/main

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.86 %
  • code
  • 95.87 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.17 %
  • line
  • 96.90 %
  • branch
  • 94.34 %
  • toggle
  • 92.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 10.000s 715.616us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 28.345us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 46.438us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 208.382us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 26.151us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 1462.426us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 46.438us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 26.151us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 350.000s 257199.910us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 124.000s 25802.727us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 38.000s 7108.542us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 228.000s 18518.610us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 185.000s 17511.445us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 87.000s 193150.820us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 60.000s 13180.220us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 57.000s 57571.326us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 687.452us 8 8 100.00
sram_ctrl_partial_access_b2b 341.000s 112230.720us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 1341.555us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1379.231us 0 8 0.00
sram_ctrl_throughput_w_readback 8.000s 2765.763us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 20.000s 5255.012us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 6743.139us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 579.000s 157578.539us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 27.447us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 139.281us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 139.281us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 28.345us 1 1 100.00
sram_ctrl_csr_rw 2.000s 46.438us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 26.151us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.091us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 28.345us 1 1 100.00
sram_ctrl_csr_rw 2.000s 46.438us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 26.151us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.091us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 37.000s 7260.277us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 8.000s 7057.791us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 438.032us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 8.000s 7057.791us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 438.032us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 20.000s 5255.012us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 20.000s 5255.012us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 46.438us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 57.000s 57571.326us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 57.000s 57571.326us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 57.000s 57571.326us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 60.000s 13180.220us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 9.000s 5097.368us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 37.000s 7260.277us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 8.000s 5529.566us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 10.000s 715.616us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 10.000s 715.616us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 57.000s 57571.326us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 8.000s 7057.791us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 60.000s 13180.220us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 8.000s 7057.791us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 7057.791us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 10.000s 715.616us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 7057.791us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 66.000s 2972.265us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 1980613044983172339412709296587993763768374185073946998418118190475110301248 86
UVM_INFO @ 1341554572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 109285268455460450949903835321133895709629956095925210641156476312761952072203 86
UVM_INFO @ 1379230881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 65464539162569113696784206349581583510558293004667040713401588476651737112051 86
UVM_INFO @ 2630678853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54663059785412867642976077191036294544484051783148810168839802300579986121619 86
UVM_INFO @ 1351818283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 56385794564355400331983162711383324114412998664942606975625271476744480825466 86
UVM_INFO @ 2638063096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2609712378668854195083272449318907072527453881057555834347799164342971241285 86
UVM_INFO @ 2855678758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 62190633602998360458013341062020147875034917977558710230207542893805835639841 86
UVM_INFO @ 5494896369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 4749171656543329420311734223230883203405781692728727324866100626839171151317 86
UVM_INFO @ 1383294416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 90290458081548087141093444945353363856111926736854647543019813898718706671456 86
UVM_INFO @ 2655195681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 40178938802312841024662003627583553777894388242352276178395152418669022954315 86
UVM_INFO @ 1350176735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 81282674891078238193845198401085495462551925945759991288498798873801729195972 86
UVM_INFO @ 658254648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 74738088839704432780147938977928872756825157857822464938286834211646298793463 86
UVM_INFO @ 7336917578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 86273825191559179552326430806914233837598504631678557967290409448142078266574 86
UVM_INFO @ 679181158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 6411935956676973711650730226407524669144262451959952136766941383812726553095 86
UVM_INFO @ 699802884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 18834287107016853834913758900816179334411921802413967843970303538199249603675 86
UVM_INFO @ 661011287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 352644193542267703945859969114615888374011610359412921581142696996350857075 86
UVM_INFO @ 2626869753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 110744439314894245383420124470568588228994371037975448093124927333248291488945 86
UVM_INFO @ 3158225820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 78292600669635460963746366355385153603482760122086254316929996877669492184082 86
UVM_INFO @ 2765762800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 66804442426430132491624689043827888931986768571638851507673781606366238506321 86
UVM_INFO @ 676293252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 5767832709680554206475128121030234109827222118560434141415906316272669478802 86
UVM_INFO @ 1326494029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 11032529908999305299526724150321655075541845651897057673061320951124335826540 86
UVM_INFO @ 1443702631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 39015614074675141729965547089675817576045353840423731440836527964143651599295 86
UVM_INFO @ 2761855866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 95987180658075264744058545336647930147454109115758869334327702375280661014518 86
UVM_INFO @ 697552841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 80491800624735340136974433742690739469312672938230883898689233437922751860619 86
UVM_INFO @ 1391891860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---