Simulation Results

Simulation Results: sysrst_ctrl

04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.41 %

code
98.51 %

assert
98.85 %

func
91.86 %

line
99.46 %

branch
99.56 %

cond
98.04 %

toggle
100.00 %

FSM
95.51 %

Validation stages

V1		100.00%
V2		97.90%
V2S		100.00%
V3		90.00%

43/43 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	6.790s	2110.804us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	8.390s	2476.836us	10	10	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	8.000s	2420.971us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.540s	2535.031us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	3.550s	4035.168us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	7.380s	2065.323us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	122.970s	75487.784us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	6.190s	2549.160us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.160s	2089.896us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	7.380s	2065.323us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.190s	2549.160us	1	1	100.00

327/334 passed

97.90 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				25	25	100.00
	sysrst_ctrl_combo_detect	364.670s	179732.566us	25	25	100.00
combo_detect_with_pre_cond				95	100	95.00
	sysrst_ctrl_combo_detect_with_pre_cond	711.320s	319507.064us	95	100	95.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	331.770s	149098.209us	25	25	100.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	272.420s	1094182.794us	50	50	100.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	9.270s	2510.955us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	7.840s	2105.473us	10	10	100.00
ec_power_on_reset				10	10	100.00
	sysrst_ctrl_ec_pwr_on_rst	14.410s	4605.394us	10	10	100.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	9.480s	2608.579us	10	10	100.00
ultra_low_power_test				24	25	96.00
	sysrst_ctrl_ultra_low_pwr	154.810s	975720.643us	24	25	96.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	39.510s	34753.695us	2	2	100.00
stress_all				9	10	90.00
	sysrst_ctrl_stress_all	116.600s	46171.089us	9	10	90.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	7.300s	2009.428us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	7.120s	2010.819us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sysrst_ctrl_tl_errors	8.870s	2044.270us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sysrst_ctrl_tl_errors	8.870s	2044.270us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	3.550s	4035.168us	1	1	100.00
	sysrst_ctrl_csr_rw	7.380s	2065.323us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.190s	2549.160us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	23.220s	7964.629us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	3.550s	4035.168us	1	1	100.00
	sysrst_ctrl_csr_rw	7.380s	2065.323us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.190s	2549.160us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	23.220s	7964.629us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	sysrst_ctrl_sec_cm	97.580s	42010.276us	5	5	100.00
	sysrst_ctrl_tl_intg_err	121.420s	42464.987us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	sysrst_ctrl_tl_intg_err	121.420s	42464.987us	25	25	100.00

9/10 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				9	10	90.00
	sysrst_ctrl_stress_all_with_rand_reset	18.270s	22982.202us	9	10	90.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				3 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	83373826269884958873946189148392431484553437224703645539579236556754836617003	680	UVM_ERROR @ 24700966963 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o UVM_INFO @ 24700966963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	84560859719502445292142549214404537845352418386905921553450149320085160127479	702	UVM_ERROR @ 50153327614 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 50153327614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	66011698871602563916557445104495067582758293063110492442086385512456730325657	683	UVM_ERROR @ 43572345832 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 43572345832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				2 test runs
	sysrst_ctrl_stress_all_with_rand_reset	60286795328896300447035293247244634790665095355625528770729938389121450977668	686	UVM_INFO @ 15420246742 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 16045246742 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 16076290724 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_in_out_inverted_vseq UVM_INFO @ 17302704106 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
	sysrst_ctrl_ultra_low_pwr	25775432292742641810416922038103335437843300095332694372061904451036959581452	656	UVM_INFO @ 6002695758 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_INFO @ 7657695758 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 7688675459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value:				1 test run
	sysrst_ctrl_stress_all	71185803940970464184204240974196230862248048833599080777120485104907747124538	664	UVM_INFO @ 9269764434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	13412562702133190837520926496771304713720983542062952361935866392936984598757	750	UVM_INFO @ 161972484336 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 161992484336 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 172070604116 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e UVM_INFO @ 172070754116 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x128
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	71038512866734340486751443744821159848984020662339730424063876649280781144855	663	UVM_ERROR @ 13155263854 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4 UVM_INFO @ 13155263854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---