Simulation Results: uart

 
04/07/2026 02:41:51 DVSim: v1.49.0 sha: 98a020b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.81 %
  • code
  • 92.64 %
  • assert
  • 98.56 %
  • func
  • 99.23 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
96.47%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 16.370s 5911.919us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.900s 56.810us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.970s 26.726us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.020s 142.172us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.190s 31.424us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.160s 178.065us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.970s 26.726us 5 5 100.00
uart_csr_aliasing 1.190s 31.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 56.690s 40871.503us 10 10 100.00
parity 20 20 100.00
uart_smoke 16.370s 5911.919us 10 10 100.00
uart_tx_rx 56.690s 40871.503us 10 10 100.00
parity_error 20 20 100.00
uart_intr 79.050s 133285.712us 10 10 100.00
uart_rx_parity_err 226.090s 114504.047us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 56.690s 40871.503us 10 10 100.00
uart_intr 79.050s 133285.712us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 124.230s 103074.002us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 85.860s 134414.370us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 290.820s 150556.420us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 79.050s 133285.712us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 79.050s 133285.712us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 79.050s 133285.712us 10 10 100.00
perf 9 10 90.00
uart_perf 503.420s 16303.730us 9 10 90.00
sys_loopback 10 10 100.00
uart_loopback 11.970s 8188.396us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 11.970s 8188.396us 10 10 100.00
rx_noise_filter 1 10 10.00
uart_noise_filter 54.920s 76196.005us 1 10 10.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 23.600s 45502.447us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 13.320s 7410.581us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 31.740s 7043.280us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 347.440s 85797.175us 10 10 100.00
stress_all 6 10 60.00
uart_stress_all 1184.120s 273239.073us 6 10 60.00
alert_test 10 10 100.00
uart_alert_test 0.930s 41.837us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.940s 12.259us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.810s 1104.909us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.810s 1104.909us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.900s 56.810us 1 1 100.00
uart_csr_rw 0.970s 26.726us 5 5 100.00
uart_csr_aliasing 1.190s 31.424us 1 1 100.00
uart_same_csr_outstanding 1.190s 138.271us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.900s 56.810us 1 1 100.00
uart_csr_rw 0.970s 26.726us 5 5 100.00
uart_csr_aliasing 1.190s 31.424us 1 1 100.00
uart_same_csr_outstanding 1.190s 138.271us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.250s 255.824us 5 5 100.00
uart_tl_intg_err 1.990s 349.949us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.990s 349.949us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
uart_stress_all_with_rand_reset 60.600s 22606.535us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 8 test runs
uart_noise_filter 2626717796058372114317531115700846143412900862601598729891457789395017181504 75
UVM_ERROR @ 3390715425 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 4547675557 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4547869433 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4548063309 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 58696051908995122161060765418390605295113044174513867163824296209447274423361 75
UVM_ERROR @ 554487115 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 554537115 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 554562115 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 554612115 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 77112837601383780203918775321226431919252709558443939771893349226025201467999 74
UVM_ERROR @ 60438115 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 60438115 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 61207355 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 61207355 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 86961836813227659181298546356017451240111347544415780776839132030171887989600 74
UVM_ERROR @ 19341611 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 22479564 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 22686462 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 28341674 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 96891384537831462772988275756286872883896320072611409923620121215479019730991 85
UVM_ERROR @ 31066820875 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 31169296963 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 31169392201 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 31169439820 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (30 [0x1e] vs 253 [0xfd]) reg name: uart_reg_block.rdata
uart_noise_filter 102627312695439875348641529288657175790407487905726551540174666811842027285289 75
UVM_ERROR @ 5499707430 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5500019925 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5500207422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5500624082 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 110889573394861502237382083600977915811432827704157311040978873165827601664063 130
UVM_ERROR @ 78009152101 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 79073625784 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (221 [0xdd] vs 186 [0xba]) reg name: uart_reg_block.rdata
UVM_ERROR @ 79485039514 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 79485039514 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_noise_filter 55829188008378971548851114352435114346745841351674141578429968882827714033211 81
UVM_ERROR @ 74047145251 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 74374545251 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 74543605251 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 74675085251 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 3 test runs
uart_noise_filter 76250008856244647492804891752302161206104485413130112491578477912082306615882 80
UVM_ERROR @ 220444268134 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 220444823689 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (210 [0xd2] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 220445045911 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 220445379244 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (210 [0xd2] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 115640541843237076675764957859858845964675840254709588450254241217741026429026 76
UVM_ERROR @ 4808212248 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 4809087248 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (217 [0xd9] vs 111 [0x6f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4818462248 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 13, clk_pulses: 0
UVM_ERROR @ 4818712248 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 7006202462538657866555115616580434773793967685710460290502012511519375694919 76
UVM_ERROR @ 14729151059 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 14730551059 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (62 [0x3e] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 15582151059 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 23, clk_pulses: 0
UVM_ERROR @ 15582551059 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 2 test runs
uart_stress_all 38645670053970676676747462373076699642087877807644589365517543649312400812291 75
UVM_ERROR @ 1380570 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
UVM_INFO @ 1210520664 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/6
UVM_INFO @ 1523429644 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/6
UVM_INFO @ 4458836316 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/6
uart_perf 1717735315375728463710695321964053303519773039041106345484659086944329635460 74
UVM_INFO @ 3112230627 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
UVM_INFO @ 5153649744 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
UVM_INFO @ 8773867845 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
UVM_INFO @ 8779467873 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_stress_all 39622566144015427838855422724181417329369952566996018678169905448223612791775 75
UVM_ERROR @ 180077779 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 184869484 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 184869484 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 595706104 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_FATAL (cip_base_vseq.sv:465) [uart_common_vseq] wait timeout occurred! 1 test run
uart_stress_all_with_rand_reset 59530770825501009103154886591592355499656749655734071122751276340573108370562 111
UVM_INFO @ 11430698832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---