Simulation Results

Simulation Results: adc_ctrl

11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.44 %

code
96.15 %

assert
92.54 %

func
13.64 %

line
98.89 %

branch
97.46 %

cond
87.55 %

toggle
99.53 %

FSM
97.30 %

Validation stages

V1		100.00%
V2		50.28%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	16.930s	5908.738us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	3.930s	1211.183us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.460s	558.666us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	57.820s	26571.934us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.780s	828.675us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.460s	515.765us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.460s	558.666us	5	5	100.00
	adc_ctrl_csr_aliasing	3.780s	828.675us	1	1	100.00

89/177 passed

50.28 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.000s	473.212us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.180s	475.275us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.180s	446.816us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.030s	402.929us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	1.930s	408.039us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	1.970s	420.169us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.170s	470.280us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	1.680s	356.470us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	12.640s	4085.876us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	63.710s	46795.005us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	213.600s	117613.842us	10	10	100.00
stress_all				2	10	20.00
	adc_ctrl_stress_all	152.550s	100062.317us	2	10	20.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.140s	469.787us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	1.420s	423.719us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.510s	619.079us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.510s	619.079us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	3.930s	1211.183us	1	1	100.00
	adc_ctrl_csr_rw	2.460s	558.666us	5	5	100.00
	adc_ctrl_csr_aliasing	3.780s	828.675us	1	1	100.00
	adc_ctrl_same_csr_outstanding	14.710s	5404.391us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	3.930s	1211.183us	1	1	100.00
	adc_ctrl_csr_rw	2.460s	558.666us	5	5	100.00
	adc_ctrl_csr_aliasing	3.780s	828.675us	1	1	100.00
	adc_ctrl_same_csr_outstanding	14.710s	5404.391us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	19.730s	8217.634us	5	5	100.00
	adc_ctrl_tl_intg_err	25.600s	8613.701us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	25.600s	8613.701us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	5.450s	9142.752us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				97 test runs
	adc_ctrl_filters_polled	28223721206657848017555086395896795109201197759042998830821709627492863306236	386	UVM_INFO @ 482568198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	100795873467677925589361472083577221715628427375396280962647205278874575246777	386	UVM_INFO @ 384826791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	112686573388470774222936765676271099992815509932091131592465027714991794331839	386	UVM_INFO @ 424254754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	107723891276099506021339973988470595133782751884691190878605882139507955925932	386	UVM_INFO @ 424752034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	64099262970766965511558027595423231769434787914913294134408523967334507478427	386	UVM_INFO @ 322661612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	114544032722086318617896868659391507997825544429379962529053863257433573819967	386	UVM_INFO @ 420168720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	113414517260205226609192207323329669026818755853190656644392319766084336939018	386	UVM_INFO @ 549903764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	45934866639321455319479475835206604766390997293078819925257718965147788324711	386	UVM_INFO @ 318436840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	29881454391495871176810941222898667686628555475712143686446101165777841757997	416	UVM_INFO @ 1555756656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	43038243512734442447960709025680090229649282904876021117795803633709921918907	399	UVM_INFO @ 5500001420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	101767463497531875544666683237896701253921457665723310057691405792227721185826	386	UVM_INFO @ 291132453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	94620514596761419124483523546983098560243220935276510070300673156723986094519	386	UVM_INFO @ 310963377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	2268001597070677970476563851032376369676677361695525045343916060437746629639	386	UVM_INFO @ 501740352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	62278796172642841588623173934654104375729478896986294663989214523442135078095	386	UVM_INFO @ 377388181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	93168030161603156003892246226799480134976122684903344736265903120146458974913	386	UVM_INFO @ 358672554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	27793492601398631389795901512133290039826662794139875979946194420559946097451	386	UVM_INFO @ 402154286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	90856872856010029043157079331825715685000357637553617780394986473193399496072	386	UVM_INFO @ 292654099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	100700740130035786383292314978418933000056164117982136343225040359421808297596	386	UVM_INFO @ 396587855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	61440597623050403268020071686007616099339594891004646137773254355764444350859	406	UVM_INFO @ 942306794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	106186887701343549233093248562714897850769103322161351689671136680377158857545	387	UVM_INFO @ 775100964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	21807214159883753318731524961988411624948893531763678792884066619239206962941	386	UVM_INFO @ 351618250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	3704742354777284155210157837637934909712387434174225838987943358793052490531	386	UVM_INFO @ 475274754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	9028002702264513758081766571205919062430596765238718438677386429315399534324	386	UVM_INFO @ 446816447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	56382984279324640910691654340972770869200098261602200543419156767517303292657	386	UVM_INFO @ 486320495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	96127000355444176260527774883375550020956306933787831723985086871945798890252	386	UVM_INFO @ 350058306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	34355631403676586961175798102502684672678817034712913447673881271711495488396	386	UVM_INFO @ 428562923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	34565309273336267518205936876706357343281254150528369633465808665569278869659	386	UVM_INFO @ 344854801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	14759833379075393109182200834402464251030327045945089680834195811173976125114	386	UVM_INFO @ 502845112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	46844141406443400695909404399956955812617706362666840421242367818845347672936	399	UVM_INFO @ 1175610343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	100703851124519043467303424688382736529083691990097704820208272962073303760524	387	UVM_INFO @ 733058601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	29641988718284994661831146701847441842844226554681151276802752676396740043111	386	UVM_INFO @ 311835211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	34502475233791108227757320932901335560785902727188433578437488603883261433503	386	UVM_INFO @ 415921525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	41939502878953134727000091391482130796087473853885928157016149007583941026658	386	UVM_INFO @ 286775813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	6154705487458038709980284874896311279436680652298414063439543638180790097175	386	UVM_INFO @ 436621006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	77352678266841196797603259282876882649946268052353258702254673126337107960650	386	UVM_INFO @ 367267343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	70262769971087676433036230233218671136562554595706031924345805804196182989224	386	UVM_INFO @ 334175068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	83088449207276113759243622156219646618794348066132873378938017651951831584199	386	UVM_INFO @ 296702161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	60322876915733999721805430297534546751126218545284940506818019065975730127329	386	UVM_INFO @ 460604983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	28088100495606107451666431588650355513747711698760191336957270578155259195962	420	UVM_INFO @ 1810839280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	44975977338174012322432289924094988748574602148038224385131243742596887708815	386	UVM_INFO @ 429521386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	5794289623093890177676321945607784970637751766771964676194481595515835383995	386	UVM_INFO @ 380838420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	90955058109782925673844527545342265644513270763450799207687798710981579301262	386	UVM_INFO @ 481888574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	72304575816660618807470109833221328681964642222179046883314876759548177265225	386	UVM_INFO @ 360879655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	7361297081582879288374680887297037408282856647903616098869339092579278684842	386	UVM_INFO @ 282217737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	29761203625008773172686227071903165147942272087933203019748876298938645382709	386	UVM_INFO @ 475854012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	48175565376030386386360071178918255302225563476489541712595630028113473125032	386	UVM_INFO @ 446686422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	14438473264924106411158218891589710759190443377619306585003689583992830218249	386	UVM_INFO @ 380945541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	68812136917173350520488378903612419544637164403824181489374482821603487697077	392	UVM_INFO @ 761974957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	16109956078485765900529029585628932380205780942554475776562477876420777397436	387	UVM_INFO @ 857266524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	98081996743955145367100585409017131211238460360476915084610648924770894970228	386	UVM_INFO @ 476920091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	98578813762292963797985205686149224732348264133964480065778584998016239931542	386	UVM_INFO @ 411770896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	17324790858077119297996615711587668522868450931484191677825540217243915274262	386	UVM_INFO @ 349549504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	16476132218885491418950436129434292219249957962677155997793639435988936566667	386	UVM_INFO @ 491337446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	17250985317177614760914991042840723072815050771096594674601669530412686824928	386	UVM_INFO @ 408039055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	77902776410804742911180828791600209077303100302773010871484350229931190205804	386	UVM_INFO @ 521316121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	15348819126110057261234880406680023216567070854357633141393799921084133595441	386	UVM_INFO @ 274784097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	60370377604807322622679698981069282820593441114159207645376932723853785375790	386	UVM_INFO @ 420176644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	61342008178065618668615208936761653421314751272194789069994608001321665099901	399	UVM_INFO @ 2039311244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	98219171594756400770831888878960030943735730259671017825934481872159096175150	386	UVM_INFO @ 401165987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	96569781091623033230222808278486044841071498282400678764190362088114476161780	386	UVM_INFO @ 345590502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	16310316726055495175877743670460108929893246864007362974720330737988509486555	386	UVM_INFO @ 321589776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	87928884352039392901895325176658122039995045334366510536483782890523681044704	386	UVM_INFO @ 425976982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	55201565178596205915352114934354618434446019680620559556483905618707762435833	386	UVM_INFO @ 394910913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	62904786708712925527437509018277715905988873345925625374881138277775693640886	386	UVM_INFO @ 400404091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	114905556662718154154080153462041093904464852502218708683345596476922008654555	386	UVM_INFO @ 367790375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	33666602134329129834280210233914861376330066462008330940624676567152430351443	386	UVM_INFO @ 445489351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	95733666490880036881067609696617131232387821448041713661380031974077049450739	392	UVM_INFO @ 850700675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	82548419807441018406677818456015200677114001743308232101020398631484056264151	426	UVM_INFO @ 100062316577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	17596717381883103200700667801042203087610795997394313208347050403436192796782	386	UVM_INFO @ 319392957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	30817557701982247688987353021647096365533606539870946720229094469172874090373	386	UVM_INFO @ 377461965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	101244341090007818047163472501443330544077964295180839545340963127420339068817	386	UVM_INFO @ 356584853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	50170390386859982587134353107195542726559995505194640859401437950127378240425	386	UVM_INFO @ 526903271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	12321829042117919668128426803565363626784272426831528854637968324898057766854	386	UVM_INFO @ 314671937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	52180568978591720124886296001888400893168934120221909000476899445961285454905	386	UVM_INFO @ 458771480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	100246303845652927820226924885565339474328218753714136684927125482896865927679	386	UVM_INFO @ 304987043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	85311719149591591863574044896803937799308318173109959523210287844655237040208	386	UVM_INFO @ 419673002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	94021925610083755389556684911858807659141159341095606265978559874384096451170	387	UVM_INFO @ 877889614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	11581725280710610943601244507354785326095528061845040244697111092340511605236	386	UVM_INFO @ 473212496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	111202291077752607431448837321461774607665984210323634798691229835252556396859	386	UVM_INFO @ 508825438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	16673143119307706842544023406353258941933635246102744714661394880576205139342	386	UVM_INFO @ 283594945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	5210588335787812137495882353766563068504768296629006472164080405778002265079	386	UVM_INFO @ 402929124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	98927473045501273157742796947366151329167603989193961025803806106392160950794	386	UVM_INFO @ 288230328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	99665393968266782011722111532638482030080274871481289033207519436748196777125	386	UVM_INFO @ 288665963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	105216275474756322418919460119634391247166486909238580409094175235979614566454	386	UVM_INFO @ 444239004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	6229530796442076225409911021502915582157963586030909863816841969237439557325	386	UVM_INFO @ 470280468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	24136032880902371867619968747278166653658416942782438936844062985460576318024	392	UVM_INFO @ 815431664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	11922547450990721450159494854851336368567114994013776713278308177088707032293	387	UVM_INFO @ 736535048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	16950103469810025119424615990442306515893746279503907403420163573642156098868	386	UVM_INFO @ 318862161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	109901469423253553739477965071828627522366835171061395787346017235253426024644	386	UVM_INFO @ 442983346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	111925425611162439232405793827074150036668373771030690126028762001567092747511	386	UVM_INFO @ 439739707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	92727241976506387864336729130577001534552585607415853969407247226358899625961	386	UVM_INFO @ 305425951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	64205482838102068238914019055402670626096833909080045478834991322557900017783	386	UVM_INFO @ 284458225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	102809842520848328618615426561670396882224014280162951424034450552322998654950	386	UVM_INFO @ 292823358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	87298058045601745422614667984600301076487584479782760914277288737320803893809	386	UVM_INFO @ 356470338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	34015479182352381568663607280982835625623877225698844408212405152040716588148	386	UVM_INFO @ 386018393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	59282196279080828516148714503177759563803130408610162153388960735709072329814	392	UVM_INFO @ 880840847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	79536485130917781263644370268673756831197914572504912057159432832557576636031	387	UVM_INFO @ 755493374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---