| V1 |
|
100.00% |
| V2 |
|
89.55% |
| V2S |
|
99.02% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 45.790s | 787.016us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 6.190s | 132.599us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 10.850s | 262.221us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 450.300s | 37502.317us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 185.660s | 4346.104us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 15.040s | 179.294us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 10.850s | 262.221us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 185.660s | 4346.104us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 248.650s | 4530.594us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 69.200s | 1281.850us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2837.450s | 260525.267us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 68.740s | 4831.282us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 45.790s | 787.016us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 67.570s | 1271.904us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 81.930s | 5882.816us | 50 | 50 | 100.00 | |
| ping_timeout | 20 | 50 | 40.00 | |||
| alert_handler_ping_timeout | 511.320s | 167711.231us | 20 | 50 | 40.00 | |
| lpg | 97 | 100 | 97.00 | |||
| alert_handler_lpg | 2871.580s | 71773.859us | 48 | 50 | 96.00 | |
| alert_handler_lpg_stub_clk | 3040.470s | 1000000.000us | 49 | 50 | 98.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 3958.260s | 553907.760us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 17.950s | 781.135us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.070s | 669.974us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.290s | 93.262us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 25.060s | 322.640us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 25.060s | 322.640us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 6.190s | 132.599us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 10.850s | 262.221us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 185.660s | 4346.104us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 51.140s | 3044.574us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 6.190s | 132.599us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 10.850s | 262.221us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 185.660s | 4346.104us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 51.140s | 3044.574us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 316.690s | 5303.649us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 316.690s | 5303.649us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 316.690s | 5303.649us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 316.690s | 5303.649us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1003.530s | 17360.054us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 82.120s | 5846.903us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 82.120s | 5846.903us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 316.690s | 5303.649us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 45.790s | 787.016us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 45.790s | 787.016us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 45.790s | 787.016us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 45.790s | 787.016us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 68.740s | 4831.282us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 48 | 50 | 96.00 | |||
| alert_handler_lpg | 2871.580s | 71773.859us | 48 | 50 | 96.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 68.740s | 4831.282us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2837.450s | 260525.267us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2837.450s | 260525.267us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 29.810s | 523.924us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 10 | 50.00 | |||
| alert_handler_stress_all_with_rand_reset | 347.830s | 19476.709us | 5 | 10 | 50.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 25 test runs | |||
| alert_handler_ping_timeout | 63341673064102046424399050980916666246386714421940783376324129122013308130121 | 90 |
UVM_INFO @ 14670466878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53585261751063274958787207127114722861719271215822863301016189137035236317900 | 87 |
UVM_INFO @ 1808440259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 109446336770505432378654012617540485896770008306191583589935978009346614342006 | 99 |
UVM_INFO @ 16183214496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 51833762739252742324746311813643374017064161840391931240306007647848420246748 | 108 |
UVM_INFO @ 37453129249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 79813810133092475966445919643501083903849138413320574020235060808191367255269 | 111 |
UVM_INFO @ 4765270784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 94825391403325277219985784308928898450424145758811126782733136788097258897642 | 105 |
UVM_INFO @ 13662638853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 65794238511104586309661394733243863584109095736239533403799189060122087305035 | 87 |
UVM_INFO @ 928402321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 12362622320589910499270725363448245066510177187648889284942398223307478372881 | 102 |
UVM_INFO @ 19154980757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108622168164449607311363209350296806003950823708338251230123630638399506825771 | 102 |
UVM_INFO @ 6187319853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 61844004522787511068361291867155814728112445875066235986891922712120963977025 | 96 |
UVM_INFO @ 12552905179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 48027398042618897780998406059632150873678015607567269738163241051317184021795 | 125 |
UVM_INFO @ 8479980089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 85013293472512322390601714153792616103809749301178819039858035621625633573530 | 99 |
UVM_INFO @ 25801863656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 81734803188432507503426541809632412890608285626929534393559249192815213463070 | 129 |
UVM_INFO @ 12561579779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82853804692711228678105607225352069738140708025949112616077048558784459166562 | 90 |
UVM_INFO @ 5158802867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 24124748246810135377325725728500109367775835058354952092306129343114201592301 | 84 |
UVM_INFO @ 4953849787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 66284813115580235709555132676921653819242726936268786930507725433928649716418 | 93 |
UVM_INFO @ 6147446957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 22912534130038249672027706523786313519351147139026676175710662092924976961344 | 96 |
UVM_INFO @ 2422182998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 107361642247878194610135105847621141101348083678487382034749938151857823395780 | 102 |
UVM_INFO @ 65227575252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82894654793703016905623632745930889404626060620821959578954653422270299236590 | 88 |
UVM_INFO @ 3369061524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 43825550090883168182735223853409763065499245669347897211773167505682993154586 | 105 |
UVM_INFO @ 14894427929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 62498884942615288868739888839435130637278389032248059016191894963821077221601 | 87 |
UVM_INFO @ 5178440463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 67085137225090481979491635097570027242413736688617064422397902063092734691390 | 102 |
UVM_INFO @ 4825650189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55174650781788593587421229811872325072116170257537148343421360384606938102079 | 102 |
UVM_INFO @ 10920337139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70305771184675025205548327006198116694026134434584793174187101860513271806747 | 105 |
UVM_INFO @ 17535385735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40902314874504184085449013842503812582714352615420576700439811255066841778226 | 96 |
UVM_INFO @ 10357085179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 102420917797870978137942326052749362250867780054985155731997308296360547649372 | 174 |
UVM_INFO @ 208198697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 4034291601504987131384244534389813049369812832722410234426363040977188893494 | 172 |
UVM_INFO @ 276765022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 96117327486831737683815492893772070154134597661769378281868448063483025675041 | 198 |
UVM_INFO @ 706589899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 13290185312606910590352113816047962484841058785706725023043570089741211713674 | 180 |
UVM_INFO @ 356603069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 57364780714805992209608559466196463369311753866069859749363597629368222828311 | 194 |
UVM_INFO @ 91725008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 33732873262267041107874000245207311866943149580879793930030368140728035945069 | 182 |
UVM_INFO @ 392824357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 62551173594872636124984989465525312801991630023469977667089846271772417087388 | 168 |
UVM_INFO @ 195787025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 103806496540144802025699135160184327686728725957530757786780901819763436796627 | 182 |
UVM_INFO @ 140695208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 92693998551297315117087456173133260317151320684841479589456589234349977097846 | 198 |
UVM_INFO @ 282628289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 49187610038557229567863263412288165791891501740929193515549122056025732028629 | 178 |
UVM_INFO @ 781135156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 98690715606382313954274332883262672684450073887189865471363560917339968668664 | 146 |
UVM_INFO @ 111404530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 29477814912231264448094013714888599223446130562564684419079332239543986480538 | 170 |
UVM_INFO @ 495602529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 7581512467077580520595432784306155143992592571272967957929730017137121185788 | 144 |
UVM_INFO @ 1606543863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 71669637522962919972626077648410209023022706834296904954730570007728814393511 | 190 |
UVM_INFO @ 748848985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 76952239260857920170796405355029277084360208183174548539861499637478998221929 | 188 |
UVM_INFO @ 404554325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 19575991953647133745075034782601344379877693229239780901698725533382353602191 | 188 |
UVM_INFO @ 341463431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 44259159345684574965897836706668327399855927990692312321236007386113297010885 | 196 |
UVM_INFO @ 477687423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 35472787800498893122588942107438538110479323932774241655119046085968306618750 | 176 |
UVM_INFO @ 1076640228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 8223354345008698505617530709811879324343445260737044618183116678079548196336 | 176 |
UVM_INFO @ 145526439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 21484083795890150534550178518058838921731846052665939336761296778933169651314 | 192 |
UVM_INFO @ 1211940098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 5 test runs | |||
| alert_handler_lpg | 12939081098635010467039297436416864246718048613852034713769975570616050571602 | 80 |
UVM_INFO @ 44567428214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 62825394065828789571420942261410633050850344238551773896690380877052285211989 | 80 |
UVM_INFO @ 296392414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 4009779128334008255234026455485734222314109165896771075416001230607542990157 | 80 |
UVM_INFO @ 813595552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70590414209164574088629141527222108327386524704388710868559790332281679349441 | 81 |
UVM_INFO @ 837146131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 32292643309209927347766152575992645945315760772768243092233730614494084557334 | 80 |
UVM_INFO @ 137356043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 5 test runs | |||
| alert_handler_stress_all_with_rand_reset | 7446564548319191566508604300073817481610629328901372776859953085596085517416 | 83 |
UVM_INFO @ 111316828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 60569666327247136493360200048192424815813310663618154043991329107626429777513 | 83 |
UVM_INFO @ 224711571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 53268661772621773261812373559759800160642069399048798555065072357721684833450 | 100 |
UVM_INFO @ 8265809024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 40519454587211060412951245589822573604076357386897776838049429828402243889198 | 131 |
UVM_INFO @ 3038870682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 35375673083745451131663796390726010110745772348744833040839458908875132927690 | 92 |
UVM_INFO @ 2527053632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt | 1 test run | |||
| alert_handler_lpg | 63579440074744683399787459841659853156397860323373388677636386719921040769327 | 83 |
UVM_INFO @ 379668877345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt | 1 test run | |||
| alert_handler_ping_timeout | 65966261914210444053811988166453947507969893480569628477879501464888671347745 | 88 |
UVM_INFO @ 5698130781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_lpg_stub_clk | 12399186148152397137271885893076110669363209046858720543337314954048921517600 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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