| V1 |
|
97.66% |
| V2 |
|
85.52% |
| V2S |
|
100.00% |
| V3 |
|
86.16% |
| unmapped |
|
58.06% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 12 | 12 | 100.00 | |||
| chip_sw_example_flash | 216.420s | 3649.310us | 3 | 3 | 100.00 | |
| chip_sw_example_rom | 117.600s | 2508.486us | 3 | 3 | 100.00 | |
| chip_sw_example_manufacturer | 235.900s | 3399.071us | 3 | 3 | 100.00 | |
| chip_sw_example_concurrency | 245.750s | 3474.296us | 3 | 3 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| chip_csr_hw_reset | 193.350s | 5454.252us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| chip_csr_rw | 598.650s | 5877.737us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| chip_csr_bit_bash | 753.090s | 7240.482us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| chip_csr_aliasing | 4952.710s | 31222.553us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 2 | 5 | 40.00 | |||
| chip_csr_mem_rw_with_rand_reset | 792.020s | 10940.875us | 2 | 5 | 40.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| chip_csr_aliasing | 4952.710s | 31222.553us | 1 | 1 | 100.00 | |
| chip_csr_rw | 598.650s | 5877.737us | 5 | 5 | 100.00 | |
| xbar_smoke | 50 | 50 | 100.00 | |||
| xbar_smoke | 10.050s | 221.265us | 50 | 50 | 100.00 | |
| chip_sw_gpio_out | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 368.240s | 4119.442us | 3 | 3 | 100.00 | |
| chip_sw_gpio_in | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 368.240s | 4119.442us | 3 | 3 | 100.00 | |
| chip_sw_gpio_irq | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 368.240s | 4119.442us | 3 | 3 | 100.00 | |
| chip_sw_uart_tx_rx | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 543.920s | 4396.349us | 5 | 5 | 100.00 | |
| chip_sw_uart_rx_overflow | 20 | 20 | 100.00 | |||
| chip_sw_uart_tx_rx | 543.920s | 4396.349us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx1 | 502.150s | 4312.343us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx2 | 527.990s | 4876.308us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx3 | 537.370s | 4235.907us | 5 | 5 | 100.00 | |
| chip_sw_uart_baud_rate | 20 | 20 | 100.00 | |||
| chip_sw_uart_rand_baudrate | 2393.730s | 13333.858us | 20 | 20 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 10 | 10 | 100.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 2184.810s | 13628.835us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 937.760s | 9348.888us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 332.500s | 5185.667us | 10 | 10 | 100.00 | |
| chip_padctrl_attributes | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 332.500s | 5185.667us | 10 | 10 | 100.00 | |
| chip_sw_sleep_pin_mio_dio_val | 2 | 3 | 66.67 | |||
| chip_sw_sleep_pin_mio_dio_val | 289.970s | 3154.353us | 2 | 3 | 66.67 | |
| chip_sw_sleep_pin_wake | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_wake | 418.470s | 6372.998us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pin_retention | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_retention | 258.720s | 3591.824us | 3 | 3 | 100.00 | |
| chip_sw_tap_strap_sampling | 20 | 20 | 100.00 | |||
| chip_tap_straps_dev | 1056.010s | 12509.220us | 5 | 5 | 100.00 | |
| chip_tap_straps_testunlock0 | 603.050s | 8529.113us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 680.370s | 10742.697us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 805.270s | 10795.480us | 5 | 5 | 100.00 | |
| chip_sw_data_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 598.170s | 6198.162us | 6 | 6 | 100.00 | |
| chip_sw_instruction_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 598.170s | 6198.162us | 6 | 6 | 100.00 | |
| chip_sw_ast_clk_outputs | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 876.660s | 8499.017us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 1781.100s | 13827.171us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 504.020s | 4428.645us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 742.760s | 5721.974us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5150.420s | 19628.576us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 268.210s | 2965.773us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 769.980s | 6727.353us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 270.960s | 3693.913us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 1853.180s | 12836.913us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 254.570s | 3019.864us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 451.010s | 5342.967us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 263.980s | 3613.318us | 3 | 3 | 100.00 | |
| chip_sw_ast_usb_clk_calib | 1 | 1 | 100.00 | |||
| chip_sw_usb_ast_clk_calib | 280.510s | 3336.073us | 1 | 1 | 100.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 8 | 8 | 100.00 | |||
| chip_sw_sensor_ctrl_alert | 790.260s | 8962.918us | 5 | 5 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 371.940s | 5549.621us | 3 | 3 | 100.00 | |
| chip_sw_sensor_ctrl_ast_status | 3 | 3 | 100.00 | |||
| chip_sw_sensor_ctrl_status | 271.760s | 3235.894us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 371.940s | 5549.621us | 3 | 3 | 100.00 | |
| chip_sw_smoketest | 51 | 51 | 100.00 | |||
| chip_sw_flash_scrambling_smoketest | 229.800s | 3224.355us | 3 | 3 | 100.00 | |
| chip_sw_aes_smoketest | 274.570s | 3610.616us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_smoketest | 272.390s | 3037.517us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_smoketest | 206.960s | 2853.248us | 3 | 3 | 100.00 | |
| chip_sw_csrng_smoketest | 225.180s | 2804.267us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_smoketest | 1244.400s | 8335.944us | 3 | 3 | 100.00 | |
| chip_sw_gpio_smoketest | 241.940s | 2831.359us | 3 | 3 | 100.00 | |
| chip_sw_hmac_smoketest | 281.440s | 3328.800us | 3 | 3 | 100.00 | |
| chip_sw_kmac_smoketest | 253.890s | 3372.052us | 3 | 3 | 100.00 | |
| chip_sw_otbn_smoketest | 2155.620s | 11528.384us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 479.550s | 6789.636us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 454.010s | 6173.368us | 3 | 3 | 100.00 | |
| chip_sw_rv_plic_smoketest | 215.720s | 3019.160us | 3 | 3 | 100.00 | |
| chip_sw_rv_timer_smoketest | 205.630s | 3110.465us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_smoketest | 255.510s | 3450.581us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 210.560s | 3696.316us | 3 | 3 | 100.00 | |
| chip_sw_uart_smoketest | 236.400s | 3362.800us | 3 | 3 | 100.00 | |
| chip_sw_otp_smoketest | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_smoketest | 246.270s | 3226.712us | 3 | 3 | 100.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 523.080s | 5228.714us | 0 | 3 | 0.00 | |
| chip_sw_boot | 3 | 3 | 100.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 12411.340s | 60284.334us | 3 | 3 | 100.00 | |
| chip_sw_secure_boot | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3958.260s | 15538.576us | 3 | 3 | 100.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 30.488s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 1461.170s | 14249.299us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 1118.590s | 14849.304us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 3 | 3 | 100.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 10846.080s | 53719.231us | 3 | 3 | 100.00 | |
| chip_sw_inject_scramble_seed | 3 | 3 | 100.00 | |||
| chip_sw_inject_scramble_seed | 11654.650s | 56422.077us | 3 | 3 | 100.00 | |
| tl_d_oob_addr_access | 2 | 30 | 6.67 | |||
| chip_tl_errors | 266.500s | 3696.053us | 2 | 30 | 6.67 | |
| tl_d_illegal_access | 2 | 30 | 6.67 | |||
| chip_tl_errors | 266.500s | 3696.053us | 2 | 30 | 6.67 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 4952.710s | 31222.553us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 2916.580s | 25821.109us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 193.350s | 5454.252us | 1 | 1 | 100.00 | |
| chip_csr_rw | 598.650s | 5877.737us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 4952.710s | 31222.553us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 2916.580s | 25821.109us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 193.350s | 5454.252us | 1 | 1 | 100.00 | |
| chip_csr_rw | 598.650s | 5877.737us | 5 | 5 | 100.00 | |
| xbar_base_random_sequence | 50 | 50 | 100.00 | |||
| xbar_random | 80.090s | 2194.416us | 50 | 50 | 100.00 | |
| xbar_random_delay | 300 | 300 | 100.00 | |||
| xbar_smoke_zero_delays | 7.330s | 52.917us | 50 | 50 | 100.00 | |
| xbar_smoke_large_delays | 92.150s | 10157.261us | 50 | 50 | 100.00 | |
| xbar_smoke_slow_rsp | 82.840s | 6066.781us | 50 | 50 | 100.00 | |
| xbar_random_zero_delays | 48.140s | 623.344us | 50 | 50 | 100.00 | |
| xbar_random_large_delays | 459.000s | 56491.999us | 50 | 50 | 100.00 | |
| xbar_random_slow_rsp | 389.860s | 32274.065us | 50 | 50 | 100.00 | |
| xbar_unmapped_address | 100 | 100 | 100.00 | |||
| xbar_unmapped_addr | 49.840s | 1225.314us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 47.090s | 1221.136us | 50 | 50 | 100.00 | |
| xbar_error_cases | 100 | 100 | 100.00 | |||
| xbar_error_random | 85.220s | 2519.625us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 47.090s | 1221.136us | 50 | 50 | 100.00 | |
| xbar_all_access_same_device | 100 | 100 | 100.00 | |||
| xbar_access_same_device | 113.730s | 2952.842us | 50 | 50 | 100.00 | |
| xbar_access_same_device_slow_rsp | 802.320s | 84585.189us | 50 | 50 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 50 | 50 | 100.00 | |||
| xbar_same_source | 70.030s | 2606.388us | 50 | 50 | 100.00 | |
| xbar_stress_all | 100 | 100 | 100.00 | |||
| xbar_stress_all | 497.820s | 15068.496us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_error | 630.860s | 21517.260us | 50 | 50 | 100.00 | |
| xbar_stress_with_reset | 100 | 100 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 584.370s | 7168.166us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_reset_error | 619.450s | 8135.986us | 50 | 50 | 100.00 | |
| rom_e2e_smoke | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3958.260s | 15538.576us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_output | 0 | 3 | 0.00 | |||
| rom_e2e_shutdown_output | 756.760s | 9527.590us | 0 | 3 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 3 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 687.390s | 8006.095us | 0 | 3 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 49.457s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 9.822s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 11.638s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 10.852s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 10.712s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 52.730s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 12.009s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 11.508s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 11.739s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11.744s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 104.716s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 14.332s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 11.839s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 11.418s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 11.034s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 30.560s | 10.120us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 30.920s | 10.180us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 30.280s | 10.340us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 31.260s | 10.360us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 26.330s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 21.130s | 10.100us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 27.250s | 10.160us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 29.110s | 10.160us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 29.540s | 10.280us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 27.990s | 10.320us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 24.080s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 21.770s | 10.180us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 28.680s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 28.150s | 10.260us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 26.480s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 100.270s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 11.506s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 11.300s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 11.630s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 11.240s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 7 | 9 | 77.78 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 7933.270s | 29704.030us | 2 | 3 | 66.67 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 8126.850s | 29042.822us | 2 | 3 | 66.67 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 8017.670s | 28405.257us | 3 | 3 | 100.00 | |
| rom_e2e_static_critical | 3 | 3 | 100.00 | |||
| rom_e2e_static_critical | 4179.320s | 16884.265us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.265s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.265s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 6 | 6 | 100.00 | |||
| chip_sw_aes_enc | 240.580s | 2906.956us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 268.210s | 2965.773us | 3 | 3 | 100.00 | |
| chip_sw_aes_entropy | 3 | 3 | 100.00 | |||
| chip_sw_aes_entropy | 221.680s | 3531.978us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 3 | 3 | 100.00 | |||
| chip_sw_aes_idle | 238.210s | 2799.097us | 3 | 3 | 100.00 | |
| chip_sw_aes_sideload | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 1678.070s | 10487.610us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 207.740s | 3297.940us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 539.100s | 5801.629us | 3 | 3 | 100.00 | |
| chip_sw_all_escalation_resets | 95 | 100 | 95.00 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| chip_sw_alert_handler_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 637.820s | 5880.605us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 371.810s | 3785.318us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 483.110s | 4134.595us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_entropy | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_entropy | 305.500s | 3219.936us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_crashdump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1694.670s | 12764.452us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_timeout | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 579.390s | 6582.045us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 277.270s | 3419.597us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 14400.168s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1323.570s | 7909.874us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1495.470s | 7801.089us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_ok | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_ok | 1047.290s | 7869.591us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 2 | 3 | 66.67 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 14400.170s | 0.000us | 2 | 3 | 66.67 | |
| chip_sw_aon_timer_wakeup_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 374.270s | 4540.473us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_smoketest | 479.550s | 6789.636us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 374.270s | 4540.473us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 564.960s | 7586.066us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 564.960s | 7586.066us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 5 | 5 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 437.600s | 7359.602us | 5 | 5 | 100.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 586.670s | 5902.139us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 12 | 12 | 100.00 | |||
| chip_sw_otbn_randomness | 805.810s | 5977.384us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 238.210s | 2799.097us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_idle | 216.180s | 2755.455us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 198.220s | 3277.675us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_trans | 12 | 12 | 100.00 | |||
| chip_sw_clkmgr_off_aes_trans | 463.380s | 5240.275us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_hmac_trans | 386.060s | 4928.470us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_kmac_trans | 384.800s | 4841.279us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_otbn_trans | 492.460s | 5551.118us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_peri | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_off_peri | 1093.210s | 10730.743us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_div | 21 | 21 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 542.590s | 4227.918us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 470.050s | 4456.160us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 537.040s | 4229.122us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 517.790s | 4406.144us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 541.910s | 4274.195us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 563.750s | 4763.978us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_outputs | 876.660s | 8499.017us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 611.210s | 11943.717us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 6 | 6 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 537.040s | 4229.122us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 517.790s | 4406.144us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 504.020s | 4428.645us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 742.760s | 5721.974us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5150.420s | 19628.576us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 268.210s | 2965.773us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 769.980s | 6727.353us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 270.960s | 3693.913us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 1853.180s | 12836.913us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 254.570s | 3019.864us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 451.010s | 5342.967us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 263.980s | 3613.318us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_extended_range | 33 | 33 | 100.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 200.570s | 2977.246us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 503.930s | 4286.388us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 785.370s | 6971.928us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 5494.010s | 25062.758us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 257.130s | 3477.978us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 234.030s | 3059.128us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 1540.700s | 12805.459us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 263.640s | 4064.997us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 482.880s | 5757.072us | 3 | 3 | 100.00 | |
| chip_sw_flash_init_reduced_freq | 1349.220s | 24406.917us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 27248.720s | 174432.103us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 876.660s | 8499.017us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_sleep_frequency | 465.390s | 4616.945us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_reset_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_reset_frequency | 367.740s | 3636.783us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_escalation_reset | 95 | 100 | 95.00 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1323.570s | 7909.874us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_cmd | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3104.210s | 24764.838us | 3 | 3 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 1 | 3 | 33.33 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 319.900s | 4087.038us | 1 | 3 | 33.33 | |
| chip_sw_csrng_lc_hw_debug_en | 3 | 3 | 100.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 679.600s | 7536.370us | 3 | 3 | 100.00 | |
| chip_sw_csrng_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_csrng_kat_test | 260.040s | 3175.200us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 16 | 16 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 7502.380s | 33064.840us | 10 | 10 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 201.470s | 2601.158us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1239.170s | 7836.404us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_ast_rng_req | 201.470s | 2601.158us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_csrng | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3104.210s | 24764.838us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_kat_test | 234.630s | 3409.038us | 3 | 3 | 100.00 | |
| chip_sw_flash_init | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1823.100s | 24854.795us | 3 | 3 | 100.00 | |
| chip_sw_flash_host_access | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_access | 721.490s | 5918.788us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 742.760s | 5721.974us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_ops | 450.850s | 3984.101us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 504.020s | 4428.645us | 3 | 3 | 100.00 | |
| chip_sw_flash_rma_unlocked | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4944.870s | 43206.520us | 3 | 3 | 100.00 | |
| chip_sw_flash_scramble | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1823.100s | 24854.795us | 3 | 3 | 100.00 | |
| chip_sw_flash_idle_low_power | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 321.410s | 3491.870us | 3 | 3 | 100.00 | |
| chip_sw_flash_keymgr_seeds | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2078.690s | 13130.188us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 251.110s | 3394.976us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4944.870s | 43206.520us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 251.110s | 3394.976us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 251.110s | 3394.976us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 251.110s | 3394.976us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 251.110s | 3394.976us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 95 | 100 | 95.00 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| chip_sw_flash_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 361.310s | 8471.233us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_clock_freqs | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 712.430s | 4799.892us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_escalation_reset | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 645.950s | 6975.869us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_write_clear | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 645.950s | 6975.869us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc | 6 | 6 | 100.00 | |||
| chip_sw_hmac_enc | 275.980s | 3515.071us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 270.960s | 3693.913us | 3 | 3 | 100.00 | |
| chip_sw_hmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_hmac_enc_idle | 216.180s | 2755.455us | 3 | 3 | 100.00 | |
| chip_sw_hmac_all_configurations | 3 | 3 | 100.00 | |||
| chip_sw_hmac_oneshot | 1979.140s | 11583.957us | 3 | 3 | 100.00 | |
| chip_sw_hmac_multistream_mode | 0 | 3 | 0.00 | |||
| chip_sw_hmac_multistream | 2256.400s | 12026.834us | 0 | 3 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 9 | 9 | 100.00 | |||
| chip_sw_i2c_host_tx_rx | 603.150s | 5576.198us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 565.550s | 5305.356us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 588.060s | 5496.485us | 3 | 3 | 100.00 | |
| chip_sw_i2c_device_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_i2c_device_tx_rx | 411.290s | 4175.358us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 6 | 6 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2078.690s | 13130.188us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 1853.180s | 12836.913us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_kmac | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_kmac | 1908.210s | 11655.217us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_aes | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 1678.070s | 10487.610us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_otbn | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_sideload_otbn | 6161.270s | 20026.497us | 0 | 3 | 0.00 | |
| chip_sw_kmac_enc | 9 | 9 | 100.00 | |||
| chip_sw_kmac_mode_cshake | 216.220s | 2764.062us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac | 284.010s | 3659.260us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 254.570s | 3019.864us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_keymgr | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2078.690s | 13130.188us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_lc | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_kmac_app_rom | 3 | 3 | 100.00 | |||
| chip_sw_kmac_app_rom | 245.750s | 3147.095us | 3 | 3 | 100.00 | |
| chip_sw_kmac_entropy | 3 | 3 | 100.00 | |||
| chip_sw_kmac_entropy | 2101.130s | 11100.425us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_kmac_idle | 198.220s | 3277.675us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 539.100s | 5801.629us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_jtag_access | 15 | 15 | 100.00 | |||
| chip_tap_straps_dev | 1056.010s | 12509.220us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 680.370s | 10742.697us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 805.270s | 10795.480us | 5 | 5 | 100.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 195.210s | 2974.765us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_transitions | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_kmac_req | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_key_div | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation_prod | 2073.770s | 12209.792us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 76 | 84 | 90.48 | |||
| chip_sw_flash_ctrl_lc_rw_en | 251.110s | 3394.976us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 4944.870s | 43206.520us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 264.020s | 3604.717us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 707.000s | 6675.298us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 847.400s | 7373.681us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 791.190s | 7503.632us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2078.690s | 13130.188us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 483.950s | 9167.832us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 856.770s | 9309.785us | 3 | 3 | 100.00 | |
| chip_prim_tl_access | 361.310s | 8471.233us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 611.210s | 11943.717us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 542.590s | 4227.918us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 470.050s | 4456.160us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 537.040s | 4229.122us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 517.790s | 4406.144us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 541.910s | 4274.195us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 563.750s | 4763.978us | 3 | 3 | 100.00 | |
| chip_tap_straps_dev | 1056.010s | 12509.220us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 680.370s | 10742.697us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 805.270s | 10795.480us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 285.440s | 6976.669us | 1 | 3 | 33.33 | |
| chip_lc_scrap | 6 | 6 | 100.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 258.610s | 3069.477us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 131.770s | 3414.157us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 102.660s | 2728.215us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 218.890s | 3892.655us | 3 | 3 | 100.00 | |
| chip_lc_test_locked | 3 | 6 | 50.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 2925.890s | 49634.603us | 2 | 3 | 66.67 | |
| chip_rv_dm_lc_disabled | 285.440s | 6976.669us | 1 | 3 | 33.33 | |
| chip_sw_lc_walkthrough | 4 | 15 | 26.67 | |||
| chip_sw_lc_walkthrough_dev | 914.910s | 10498.053us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 917.310s | 10689.688us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 1121.170s | 26349.700us | 2 | 3 | 66.67 | |
| chip_sw_lc_walkthrough_rma | 604.020s | 6715.158us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 2925.890s | 49634.603us | 2 | 3 | 66.67 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 6 | 9 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 90.900s | 2402.679us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 85.030s | 2676.382us | 3 | 3 | 100.00 | |
| rom_volatile_raw_unlock | 23.733s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 6 | 6 | 100.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 5073.880s | 17083.968us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5150.420s | 19628.576us | 3 | 3 | 100.00 | |
| chip_sw_otbn_rnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 805.810s | 5977.384us | 3 | 3 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 805.810s | 5977.384us | 3 | 3 | 100.00 | |
| chip_sw_otbn_idle | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 805.810s | 5977.384us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 409.480s | 3965.324us | 3 | 3 | 100.00 | |
| chip_otp_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_keys | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1823.100s | 24854.795us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 409.480s | 3965.324us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2078.690s | 13130.188us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 518.200s | 5335.307us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 275.990s | 3434.773us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1823.100s | 24854.795us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 409.480s | 3965.324us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2078.690s | 13130.188us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 518.200s | 5335.307us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 275.990s | 3434.773us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_program | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_program_error | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_program_error | 401.400s | 4921.957us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 195.210s | 2974.765us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals | 27 | 30 | 90.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 264.020s | 3604.717us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 707.000s | 6675.298us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 847.400s | 7373.681us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 791.190s | 7503.632us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 1177.020s | 14203.611us | 15 | 15 | 100.00 | |
| chip_prim_tl_access | 361.310s | 8471.233us | 3 | 3 | 100.00 | |
| chip_sw_otp_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 361.310s | 8471.233us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_dai_lock | 1 | 1 | 100.00 | |||
| chip_sw_otp_ctrl_dai_lock | 1111.660s | 7015.852us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 182.300s | 6140.069us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 1602.640s | 27862.283us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 250.410s | 6979.715us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 2 | 3 | 66.67 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 639.230s | 8172.652us | 2 | 3 | 66.67 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 529.100s | 7122.755us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 1427.200s | 23027.048us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 6 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 630.860s | 10112.583us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 564.960s | 7586.066us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 1293.110s | 14192.975us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_wdog_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_wdog_reset | 509.050s | 5046.662us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 182.300s | 6140.069us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 461.260s | 4915.150us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 2282.990s | 28760.306us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 443.190s | 7857.331us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 246.860s | 3549.989us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1989.980s | 22931.237us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 1033.750s | 8990.513us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 1392.000s | 10531.056us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2530.760s | 27824.434us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_disabled | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 257.230s | 3735.125us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_escalation_reset | 95 | 100 | 95.00 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| chip_sw_rom_access | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 483.950s | 9167.832us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 483.950s | 9167.832us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 10 | 12 | 83.33 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1392.000s | 10531.056us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1989.980s | 22931.237us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_wdog_reset | 509.050s | 5046.662us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 479.550s | 6789.636us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sys_reset_info | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 507.370s | 4538.515us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 674.110s | 7607.362us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_req_reset | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 395.690s | 5286.078us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_alert_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1694.670s | 12764.452us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_rst | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 219.620s | 2926.596us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 95 | 100 | 95.00 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1495.470s | 7801.089us | 3 | 3 | 100.00 | |
| chip_sw_nmi_irq | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 661.090s | 4474.611us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_rnd | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 746.640s | 5106.126us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 278.280s | 3491.146us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 275.990s | 3434.773us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 674.110s | 7607.362us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_double_fault | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 674.110s | 7607.362us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_mcounteren_writable | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_mcounteren_writable | 237.120s | 3415.047us | 3 | 3 | 100.00 | |
| chip_jtag_csr_rw | 3 | 3 | 100.00 | |||
| chip_jtag_csr_rw | 1444.160s | 17860.231us | 3 | 3 | 100.00 | |
| chip_jtag_mem_access | 3 | 3 | 100.00 | |||
| chip_jtag_mem_access | 1174.780s | 13878.192us | 3 | 3 | 100.00 | |
| chip_rv_dm_ndm_reset_req | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 507.370s | 4538.515us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 256.930s | 2895.853us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 2013.880s | 13782.395us | 0 | 3 | 0.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 5 | 5 | 100.00 | |||
| chip_tap_straps_rma | 680.370s | 10742.697us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 1 | 3 | 33.33 | |||
| chip_rv_dm_lc_disabled | 285.440s | 6976.669us | 1 | 3 | 33.33 | |
| chip_sw_plic_all_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 637.820s | 5880.605us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 371.810s | 3785.318us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 483.110s | 4134.595us | 3 | 3 | 100.00 | |
| chip_sw_plic_sw_irq | 3 | 3 | 100.00 | |||
| chip_sw_plic_sw_irq | 203.590s | 2861.445us | 3 | 3 | 100.00 | |
| chip_sw_timer | 3 | 3 | 100.00 | |||
| chip_sw_rv_timer_irq | 214.620s | 3518.876us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_flash_mode | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3958.260s | 15538.576us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pass_through | 459.400s | 6609.495us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 244.980s | 3320.348us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_tpm | 288.270s | 3823.385us | 3 | 3 | 100.00 | |
| chip_sw_spi_host_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_spi_host_tx_rx | 256.130s | 3292.705us | 3 | 3 | 100.00 | |
| chip_sw_sram_scrambled_access | 6 | 6 | 100.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 518.200s | 5335.307us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 451.010s | 5342.967us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents | 6 | 6 | 100.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 623.220s | 8040.927us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 656.530s | 8246.882us | 3 | 3 | 100.00 | |
| chip_sw_sram_execution | 3 | 3 | 100.00 | |||
| chip_sw_sram_ctrl_execution_main | 856.770s | 9309.785us | 3 | 3 | 100.00 | |
| chip_sw_sram_lc_escalation | 101 | 106 | 95.28 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| chip_sw_data_integrity_escalation | 598.170s | 6198.162us | 6 | 6 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 5 | 6 | 83.33 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 1033.750s | 8990.513us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 1405.980s | 23369.828us | 2 | 3 | 66.67 | |
| chip_sw_sysrst_ctrl_inputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_inputs | 292.540s | 3431.316us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_outputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_outputs | 269.880s | 3511.679us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_in_irq | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 429.750s | 4644.284us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 2 | 3 | 66.67 | |||
| chip_sw_sysrst_ctrl_reset | 1405.980s | 23369.828us | 2 | 3 | 66.67 | |
| chip_sw_sysrst_ctrl_sleep_reset | 2 | 3 | 66.67 | |||
| chip_sw_sysrst_ctrl_reset | 1405.980s | 23369.828us | 2 | 3 | 66.67 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3392.970s | 20649.096us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3392.970s | 20649.096us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 3 | 6 | 50.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 425.420s | 7449.522us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.265s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_vbus | 241.810s | 3348.634us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pullup | 206.390s | 3063.138us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_aon_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_aon_pullup | 331.140s | 3539.536us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_setup_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_setuprx | 423.270s | 4249.178us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_config_host | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_config_host | 1490.180s | 8779.426us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pincfg | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pincfg | 6801.120s | 31669.530us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_tx_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_dpi | 2355.770s | 11810.417us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_toggle_restore | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_toggle_restore | 217.640s | 2716.944us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 3 | 3 | 100.00 | |||
| chip_sw_aes_masking_off | 260.110s | 3285.014us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 214.780s | 2911.585us | 3 | 3 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 1 | 1 | 100.00 | |||
| chip_sw_coremark | 15830.190s | 68071.829us | 1 | 1 | 100.00 | |
| chip_sw_power_max_load | 3 | 3 | 100.00 | |||
| chip_sw_power_virus | 1575.500s | 6722.317us | 3 | 3 | 100.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 332.680s | 4263.856us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 1120.550s | 13834.846us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 313.750s | 4904.029us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 85.300s | 2548.178us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 112.600s | 2467.807us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 123.270s | 2858.198us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 34.389s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 395.910s | 3812.961us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_boot_mode | 464.960s | 2831.548us | 3 | 3 | 100.00 | |
| chip_sw_edn_auto_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_auto_mode | 1260.700s | 5813.049us | 3 | 3 | 100.00 | |
| chip_sw_edn_sw_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_sw_mode | 1201.020s | 7012.723us | 3 | 3 | 100.00 | |
| chip_sw_edn_kat | 3 | 3 | 100.00 | |||
| chip_sw_edn_kat | 301.560s | 2845.898us | 3 | 3 | 100.00 | |
| chip_sw_flash_memory_protection | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_mem_protection | 753.480s | 5784.984us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 234.330s | 3234.573us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 283.440s | 3235.053us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 2 | 3 | 66.67 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 479.440s | 5719.449us | 2 | 3 | 66.67 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 371.730s | 4873.916us | 3 | 3 | 100.00 | |
| chip_sw_all_resets | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1392.000s | 10531.056us | 3 | 3 | 100.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 332.680s | 4263.856us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 1120.550s | 13834.846us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 313.750s | 4904.029us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 607.270s | 6610.848us | 3 | 3 | 100.00 | |
| chip_sw_plic_alerts | 95 | 100 | 95.00 | |||
| chip_sw_all_escalation_resets | 644.790s | 5534.458us | 95 | 100 | 95.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.237s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.237s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 284.740s | 3952.422us | 3 | 3 | 100.00 | |
| chip_sw_uart_watermarks | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 543.920s | 4396.349us | 5 | 5 | 100.00 | |
| chip_sw_usbdev_stream | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_stream | 3678.550s | 18845.231us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 18 | 31 | 58.06 | |||
| chip_sival_flash_info_access | 264.490s | 3577.342us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 30.350s | 10.160us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 7.240s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_ecc_error_vendor_test | 205.130s | 2819.663us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_descrambling | 279.640s | 3400.316us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 346.030s | 4325.787us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 11.750s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 251.170s | 3578.658us | 3 | 3 | 100.00 | |
| ate_bootstrap_flash_erase | 851.950s | 10010.300us | 0 | 3 | 0.00 | |
| ate_bootstrap_one_frame | 8965.570s | 43527.276us | 3 | 3 | 100.00 | |
| ate_bootstrap_disjoint | 10800.175s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) | 90 test runs | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 44736642922487548297108073644516464562361038800626252894319825544363254294340 | 308 |
UVM_INFO @ 3000.339468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93515968386531533968053126969205254860105392635429624479158210396487089238813 | 308 |
UVM_INFO @ 3608.824392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 28215910870892712096888192976413083196814950740319533711023467333421613177206 | 308 |
UVM_INFO @ 2663.787245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 44755713706735517828674477984883435507875699381828714988373096180866175633617 | 308 |
UVM_INFO @ 3107.703006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90000878379217405978058704312904063107370165937556365005213010673718866838325 | 308 |
UVM_INFO @ 3419.596584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 61907091207070607134382229224200673817715795384448558093412497775630240755203 | 308 |
UVM_INFO @ 2360.066920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 70825153350080120027945508567426505441063539006391969633500349403136166311846 | 308 |
UVM_INFO @ 3138.867080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99037868104448810411176075366233747279099459293194137733513155303730663781020 | 308 |
UVM_INFO @ 2897.404502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16955686695967216180205641940507910127376805891820640610156250352852094181363 | 308 |
UVM_INFO @ 3182.395569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 38962225005879983190542799746839942491073510779301276250866905115264367261415 | 308 |
UVM_INFO @ 3205.087626 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 72953092265615176182796587603171740452224041181922322994335704897138984534195 | 308 |
UVM_INFO @ 2669.917568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 46439648150957906441546487642363191266824419033886379939187383998731643430760 | 308 |
UVM_INFO @ 3061.244953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 72719822745356536066036099518469880619167426789736868305028021607180157859986 | 308 |
UVM_INFO @ 2796.118526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104548779969085522097131605788673639726682747810230597497831083441320161894622 | 308 |
UVM_INFO @ 3132.090392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 48389945963840460338980267922667207225256451255663626282583804897602233635889 | 308 |
UVM_INFO @ 2620.791400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 587124079383014908524039900230846828730235205238005484294365135013657313472 | 308 |
UVM_INFO @ 2682.489320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 103946204004240448937259580122162195038084076012372707613048036897956175815351 | 308 |
UVM_INFO @ 2924.226086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 9207503052192301792352748449840655810411572877587225675020637170959557822869 | 308 |
UVM_INFO @ 2958.390819 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7996853782298420848595059985823493295917038608274111471337327744293098815497 | 308 |
UVM_INFO @ 3180.359941 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 88796532937338614768567941922938646456512522903760254545219794817764946796850 | 308 |
UVM_INFO @ 3302.743300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83554164616075752999446155226875103510927178507725429813245793138855837763707 | 308 |
UVM_INFO @ 3233.683790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111351940711633890793558567054108622534759452718558016029453423673356115499269 | 308 |
UVM_INFO @ 2865.558336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 44501898564875347833976846139769506048508384182616488795957797912658598644624 | 308 |
UVM_INFO @ 3259.463069 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 36697866137079049528151404032798796043927795932550985749806858669735896154524 | 308 |
UVM_INFO @ 2871.777866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 32401892936907655230216111530035328678641490160087931824281299910471169790006 | 308 |
UVM_INFO @ 2204.956866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 43339985643620081157139744844689456717791495649531058974473094781374239277799 | 308 |
UVM_INFO @ 3667.752548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90541659757469530330027131361841373382483537498436559482522235440822210699296 | 308 |
UVM_INFO @ 3172.089224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81047610796846937461961174350725249805321365076504930753496156565211491640725 | 308 |
UVM_INFO @ 2283.033649 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 22179964976612966617348442642344408643483044088332241842348458948796388463662 | 308 |
UVM_INFO @ 2796.373467 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 666928706437068896853114755694339612763143764870766266257961539139732924896 | 308 |
UVM_INFO @ 2805.577446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50174451461896713698660215459682325766661608144145552775318585049233344647093 | 308 |
UVM_INFO @ 2344.181678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39172068765461106098434324533228697463766021822638406370618424651490057617987 | 308 |
UVM_INFO @ 2963.291972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1823032387165561909236948104990026009508744077589285761247673697904365497018 | 308 |
UVM_INFO @ 2918.342194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60308316875621498184353086318812002041941700815056900170742964169354865578048 | 308 |
UVM_INFO @ 3016.564219 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3958243494941757907777999944008532791618236939007930614873835746529583268703 | 308 |
UVM_INFO @ 2786.634827 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 28846108556554244281404887719438909636592138644566093842654662174521874889191 | 308 |
UVM_INFO @ 2487.875310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50987018162502734761646222343670138702502620091014447450770588520679469192120 | 308 |
UVM_INFO @ 3068.985972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102186623452873038172978757994316184884524532575069494912166984269564846769879 | 308 |
UVM_INFO @ 3215.814268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64690571397278816570057473104457816113032839818257095280671759521305992935807 | 308 |
UVM_INFO @ 3100.380744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81122669611571589331296647538605107249207865637316069561563685957344215893532 | 308 |
UVM_INFO @ 2605.993729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 105471871538831710121872423388144743455270223139890342575875127435386774987429 | 308 |
UVM_INFO @ 3090.737652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 95294750497047098412623076128164743478889734995802505842700991692401426893483 | 308 |
UVM_INFO @ 3122.398504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 75339340343428567881245744745862096349367357349928129744762160814179470438105 | 308 |
UVM_INFO @ 2646.691711 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 61525723741995683831500946325265429094552408923715357948552392315945747141477 | 308 |
UVM_INFO @ 2610.782600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 45378425696822531641382048458845830547562039415128688885310195038196312077871 | 308 |
UVM_INFO @ 3405.907421 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 32755276964559225195219345255701396909746318763473931191206382173506396343234 | 308 |
UVM_INFO @ 2482.293368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2674026598787183472100430862805171412057584012728884965771334272895900286623 | 308 |
UVM_INFO @ 3240.760148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 100754764920366593051562382477802123938214703651256606107902249297749318606231 | 308 |
UVM_INFO @ 3220.596248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 40322456858355654333104256175928116361623715456528331393451604272185596177951 | 308 |
UVM_INFO @ 2810.673928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73180843201662670330225385361565419095006094680218391982010831201661312873164 | 308 |
UVM_INFO @ 2925.079012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65855110031173329260462910907434857606969034639847763567003259900562210594660 | 308 |
UVM_INFO @ 2712.412814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 119857838294380996251376661789602046677397219298702906819000763797825584899 | 308 |
UVM_INFO @ 2323.997998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99301170690645641708171637431972838072793326163983305991367058724909867928519 | 308 |
UVM_INFO @ 2743.343176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 52734390981697761733594658420665953966542564569100398698822592034582688276455 | 308 |
UVM_INFO @ 3501.587594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 52390923445452389076811614328939911118397887868897843113411248439134498905013 | 308 |
UVM_INFO @ 3201.212785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2298120988125207472536632259740992626418173322559495195600447224215132212812 | 308 |
UVM_INFO @ 2820.785950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 103534589749116873975041385314708669937184568371398382015859429063888018226376 | 308 |
UVM_INFO @ 2614.341064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29980517035404886808318204490700505620253319202502293714950513905171262235044 | 308 |
UVM_INFO @ 3182.391027 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 52616033747091415119819661005014447693140035499217580539365514921086460716735 | 308 |
UVM_INFO @ 3238.783680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 24217327267191796855621360092738897300629972062075870293723853784509911673439 | 308 |
UVM_INFO @ 2777.923999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63271861664469374075576874186423620979799858103744572692881239189003194524528 | 308 |
UVM_INFO @ 3152.542800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 110358094755589783992748286695643505450495180981538256163095672704142588119246 | 308 |
UVM_INFO @ 3250.597128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 76355445628552631896867318576534413666435229465005977791948850573966490913655 | 308 |
UVM_INFO @ 2776.230884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 19293121162559439670644314267203343669980623947226579007891427974459214999930 | 308 |
UVM_INFO @ 2947.028628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29478375965617425087602074345792699357006245303965518093808255071535014884509 | 308 |
UVM_INFO @ 3125.143784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 75180302604850061190754982846691803285767569043452719022988167004112769821728 | 308 |
UVM_INFO @ 2656.445494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12424624695339919256871712967633007921958854363794067111405755783376689686223 | 308 |
UVM_INFO @ 2854.735512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 4185059515076225563206499640336824582228424955878295134638538366876559934654 | 308 |
UVM_INFO @ 2897.325808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 5595851012842828435894047341982979601960253277743830915372418920096759325833 | 308 |
UVM_INFO @ 2587.930309 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 108322515159968814225572631730777233411730998847230840524833910021046268286227 | 308 |
UVM_INFO @ 3512.693003 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56814685023514443151240509746488838870553701400616787662132805498772311452398 | 308 |
UVM_INFO @ 3135.209683 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2888067069183552749808890884257672322409426078336496637370484288447588384324 | 308 |
UVM_INFO @ 3048.796923 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83781767672724564840224464937138233893224450894315288390110493483731725654637 | 308 |
UVM_INFO @ 2521.671362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 86435252538325731926544502868101790462653185487158352647145338071184078181807 | 308 |
UVM_INFO @ 2795.090813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99886185393357861254130176015022591138312224812033975626102825622513703803896 | 308 |
UVM_INFO @ 3448.232625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1196699391045618685386092145552014259167240338928490155621466632039910968653 | 308 |
UVM_INFO @ 2076.790585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 27417142967297468445647111971911028365431437882166648914027188378275030841216 | 308 |
UVM_INFO @ 2370.158574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 69752930947660846651410351374046534888679530316078484581584964796008513316245 | 308 |
UVM_INFO @ 2205.319430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 66604518309111940602942666142391941654607593436998515826507223134243642296185 | 308 |
UVM_INFO @ 3079.644013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 42972551930677477350340696083800442711133075465073316571104561994096848130080 | 308 |
UVM_INFO @ 3392.688773 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 98028491906128368559069226106165208097310957543902021103566513357402419434437 | 308 |
UVM_INFO @ 3389.461152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 67241242615448076541096735002322496129058091178431259082713098076691976757280 | 308 |
UVM_INFO @ 2915.495800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 66014671627390908068317104024000222038814659866432201158793152698472607934271 | 308 |
UVM_INFO @ 3077.057944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 43422560450982750385781014020810359290770207604237915231186519173681872678962 | 308 |
UVM_INFO @ 2770.841680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50711551881624473563102162151674141404955463145765201838992349382172483642318 | 308 |
UVM_INFO @ 2742.683180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73678084406566126653600906239304009159466031092605049677139944240145862006882 | 308 |
UVM_INFO @ 2968.894656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63916151579565320736230898427428930681198871679205893433991070221255435344363 | 308 |
UVM_INFO @ 2946.361085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 58914423072551018145472509605088504592657367816923998404598036060496908075154 | 308 |
UVM_INFO @ 2946.876228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 18613724288790731520526992349717735483591397868616642825387880674577401016406 | 308 |
UVM_INFO @ 2361.862292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 69700690208954380750684399522390803202146061190623426657788879696353996957975 | 308 |
UVM_INFO @ 2831.640481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 42 test runs | |||
| chip_sw_pwrmgr_sleep_wake_5_bug | 83081202571923374353764907937247747041804637985450761907549777846979539993575 | None |
---- STDERR ----
Another command (pid=3256252) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 113309654171793104068233358709703754903718483339782299273432638003195463545436 | None |
Another command (pid=278750) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=279888) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=277662) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 31407363873141305183214564508140527780782409788076223891872284111791253099932 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 67518958164625912598692971865635433398361647814009142424458446764494538457530 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 92215696921275433557414407753091320517378307694053736574154251155960144910112 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 30527450160002705174698651281363800535794074019825472490547430977614583298385 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 56519941417489521737837860506094966098776108662322268499183780629707457547222 | None |
Another command (pid=257953) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=278750) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=279888) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 63986051944702909302999525230067914827793078616836430394136396554190685513750 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 35161266565652639014050166921054069387767666613136410610318281013981863508758 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 153382052083971518702946435919903694476902421983602802661200451773409993945 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 35036404233489361012424068832599713661779403615648573115289539641877054311517 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 55984109853862412768399880858738830482913606132187519988416011056627968672113 | None |
Another command (pid=277884) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=281840) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=259764) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 50096763902879722974300261596439173675518700974503482535875850549818097269792 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 65924715838541040152233163741637221903342543805287177798384514635777370955236 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 14668470922843615168124172548488198260257736038730839918818903943138486280895 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 74546391430213158281063736967041400844558944678322300293832965573830150492933 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 94860494695360485754613001091374222186478396881604877888192686771835701644787 | None |
Another command (pid=279888) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=259477) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=261453) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 19909533011027789184929817116414543404137847691248238128404422428052298234558 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 39013838848857803812094268617863200870564047461653890484859833224093334625604 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 39843328243259587771543750636246149867550256937017562311270506574147412316450 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 32004176900705566431637397364269267485124212313376867414451556765450477407758 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 13751724409429677025736495885296843562595546916347025704820286301495272872181 | None |
Another command (pid=290583) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=298273) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=299768) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 55419468989524926895423936608598328635529132925523823736921775373653014742811 | None |
Another command (pid=297030) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=297516) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=297781) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 48314967006941614553361706677294417205349174254976339468492577530037842571393 | None |
Another command (pid=293059) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=282547) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=289037) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 64432045580523412870731615764753454136241170820625254785223293503681869266838 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 45220455748818843198029201564290634860840990128207574918778905958225802656010 | None |
---- STDERR ----
Another command (pid=286645) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 61848315346324684216972267814799993211197919868642114256798552995044940613520 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 53860962886697988943102908727858888976991377289276282232704303409509256699082 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 115210112840293452343379804843627194809154580094792785665361868907120155268448 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 39867864281891671729766150938858017198292543067126769857163799637983116145974 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 89331887297261861946289375632784918857552130210114005259299672268045821815246 | None |
---- STDERR ----
Another command (pid=333357) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=333620) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 17073034282698770567085204188964171712211623423206868752322801942133809866029 | None |
---- STDERR ----
Another command (pid=325571) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 66079279961898662415064044922805729868060301308421388498594072489889306877700 | None |
Another command (pid=322035) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=323594) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=321272) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 59946014675473317541628787378293393390283438302486285720036290958943730313950 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 73487883735642883637331136643792485259682054510482731582357741365054761833766 | None |
Another command (pid=350220) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=350482) is running. Waiting for it to complete on the server (server_pid=255015)...
Another command (pid=351351) is running. Waiting for it to complete on the server (server_pid=255015)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 66698048215467775790637367780371731472629147386064145745263749334891094920971 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 64083169962045281591170815024860157751608490165920105692346189751608551607014 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 20180055715678960067774330570004265411058102131935284006847251049490323633853 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 32779618612293881663988485797367312921833501204652145135805824629213449524796 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 56550295604530900844768522712997272159255153982065132635813169605568420496661 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 111728005832647809482832378313331267838157768657916119032303068481519256848448 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 91071833966845802096976590282604534686028671027966686033271266776194457161962 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 31 test runs | |||
| chip_tl_errors | 104472086413279211198186385156031150039052617862332938016261229845625730588501 | 217 |
TL item was: req: (cip_tl_seq_item@36286) { a_addr: 'h1058c a_data: 'hce748836 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h4 a_user: 'h1ba11 d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2306.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 73152000427315365001046388468114215763902045612963685538431275681972327023142 | 217 |
TL item was: req: (cip_tl_seq_item@30860) { a_addr: 'h10750 a_data: 'h186dfa50 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h195e9 d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2651.260600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 52039637141211833129233556919631633846975074633356652950053694978201964840608 | 217 |
TL item was: req: (cip_tl_seq_item@31108) { a_addr: 'h106ac a_data: 'hee401099 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1aecf d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2654.526828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 107732283140878479911527953687856725916417345070582019277283245377851189053462 | 224 |
TL item was: req: (cip_tl_seq_item@30312) { a_addr: 'h10458 a_data: 'h4e70bbd5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18d45 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1956.809942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 97512573335942557075257673375595525114305440018866912353973543098030159440990 | 217 |
TL item was: req: (cip_tl_seq_item@41552) { a_addr: 'h10744 a_data: 'hf75a195e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1bda2 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2279.024656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 71674799892960423386293769175691389438846059018332199876065169439505595028001 | 224 |
TL item was: req: (cip_tl_seq_item@30292) { a_addr: 'h107ac a_data: 'h98d49d03 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1a9eb d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2745.210936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 58074610364084015812102364021230620951868341623904512568062420103234522608510 | 217 |
TL item was: req: (cip_tl_seq_item@36150) { a_addr: 'h10380 a_data: 'hbd36fc3b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1ba2d d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2743.255558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 114951912647419286660706293566677657991771166172869291607337241521582512633750 | 224 |
TL item was: req: (cip_tl_seq_item@31024) { a_addr: 'h1069c a_data: 'hf7b95ee1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h192fe d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2079.672222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_tl_errors | 43213086751657538662393660950038005304815918543118489796177539283659432034930 | 218 |
TL item was: req: (cip_tl_seq_item@41460) { a_addr: 'h10504 a_data: 'h88ca6753 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h19e65 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2304.455371 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 93300947100226920448408813497366629551506571632207350019856007144940893540308 | 217 |
TL item was: req: (cip_tl_seq_item@33546) { a_addr: 'h1044c a_data: 'h5fec54fc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1a50b d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2499.170774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_tl_errors | 81711574003310239879650168604244391228795385992877292210007103011891746140879 | 217 |
TL item was: req: (cip_tl_seq_item@32928) { a_addr: 'h106f8 a_data: 'h941eeca4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1ae7d d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2051.420856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 7363880412707478893849432623697818700013620067190707744626122398703208618075 | 217 |
TL item was: req: (cip_tl_seq_item@31820) { a_addr: 'h10578 a_data: 'h9a7440cc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h19285 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2219.625754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 41946390665530108425190445822370287824039140087363286948007035913210063839679 | 217 |
TL item was: req: (cip_tl_seq_item@31688) { a_addr: 'h10348 a_data: 'h3ce3bb9b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h1b6eb d_param: 'h0 d_source: 'h21 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2862.189160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 42260471788643677469357500352508698685555874646256085238403660035426929933640 | 218 |
TL item was: req: (cip_tl_seq_item@175972) { a_addr: 'h10450 a_data: 'h1515c8fa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h199fb d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3160.118041 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 4502534874942544536153222364114449215774706521470780910441560508662842226115 | 217 |
TL item was: req: (cip_tl_seq_item@35510) { a_addr: 'h10654 a_data: 'h96d7da91 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h19e70 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2482.913639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 38874361131491062494284300298984722171508344597734969737712359895900652261430 | 217 |
TL item was: req: (cip_tl_seq_item@32928) { a_addr: 'h10654 a_data: 'h2d285535 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h19e04 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2906.171314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 8811174331113687349975032769648195080286566465439074226233554365185290586787 | 217 |
TL item was: req: (cip_tl_seq_item@30340) { a_addr: 'h104a0 a_data: 'h3412adb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1bdf8 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2318.106280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 96344547633975744883466784532378681648491868998695340756946808753949022320851 | 218 |
TL item was: req: (cip_tl_seq_item@179756) { a_addr: 'h10628 a_data: 'h8739788c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1928a d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3410.283150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_tl_errors | 46153671774051443159039110288684241416054175430308346875021448701038802416526 | 217 |
TL item was: req: (cip_tl_seq_item@37126) { a_addr: 'h10458 a_data: 'ha43e238b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h18d4b d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2518.089552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_tl_errors | 39897276455569526562447865173233322103893189228572304396185205144315597182397 | 217 |
TL item was: req: (cip_tl_seq_item@31400) { a_addr: 'h10588 a_data: 'hb4626e7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1b6b6 d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2652.584639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 1614978748437826326208544434589549254047264834263123556743733241086219429589 | 217 |
TL item was: req: (cip_tl_seq_item@33454) { a_addr: 'h104b0 a_data: 'h27ad28fc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h1993c d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2292.927099 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| chip_tl_errors | 13980750521710464238200765759332334284390080755137627101637095428941765165720 | 217 |
TL item was: req: (cip_tl_seq_item@30722) { a_addr: 'h1054c a_data: 'h6a9c90e8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1a202 d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2252.721720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 114632882149668403199467889573545534078796441633974732637144531037538066423870 | 217 |
TL item was: req: (cip_tl_seq_item@50500) { a_addr: 'h10574 a_data: 'hfd987e55 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h18a8e d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2695.127836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 21861844596065975389773305675002109914537103480517002608100832548229054658361 | 217 |
TL item was: req: (cip_tl_seq_item@31262) { a_addr: 'h104c0 a_data: 'h48748d2e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h18dd1 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2355.121300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 46237315344626195518823023172787923096637069667714400066069746552504171531424 | 217 |
TL item was: req: (cip_tl_seq_item@34796) { a_addr: 'h10338 a_data: 'hf0a7dc8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1a234 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2283.475986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 49647204693857622194002755388154588394149244615104434062165213529077902007752 | 217 |
TL item was: req: (cip_tl_seq_item@32464) { a_addr: 'h10688 a_data: 'hb97b96e1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h1ba91 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2242.702096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 93197601555552562103501281012010236961644815580467220214567463133804961142107 | 217 |
TL item was: req: (cip_tl_seq_item@37074) { a_addr: 'h10770 a_data: 'h8754f654 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h18d58 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2922.964328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 74069575474379017133746308274834090074578366221531828170455728310207449550423 | 217 |
TL item was: req: (cip_tl_seq_item@34296) { a_addr: 'h10548 a_data: 'h9bd4bbbd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1aed6 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2471.270792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 47874936350929647054343185755754953691910670598462247860484990291960682991672 | 217 |
TL item was: req: (cip_tl_seq_item@30340) { a_addr: 'h106f8 a_data: 'hee55347c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1ae43 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2317.851540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 63972346307520831180725299540257980334582019029974772662962764533667121849917 | 218 |
TL item was: req: (cip_tl_seq_item@38796) { a_addr: 'h1052c a_data: 'hd360abbb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h19219 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2486.530586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 65237131206611018685466206812346406652389229424794930986196708581035877536586 | 217 |
TL item was: req: (cip_tl_seq_item@34182) { a_addr: 'h106cc a_data: 'hcd8eb6d1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h19eca d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2502.548424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 13 test runs | |||
| chip_sw_rv_timer_systick_test | 27535192643957640267806509550981093011278868789166168468011665271457715377371 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 112783363432109777755778280354524449373396361276758686662749416493359610203751 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 81592900076836779122521993691075747100352478365509444620522962497935166619266 | None | ||
| ate_bootstrap_disjoint | 61588047652254773653808013700255826819744567083367055278971303121244429781968 | None | ||
| chip_sw_rv_timer_systick_test | 87661761143553431221531249036702444259908219994451919643755879789954755491116 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 78698961990354063340501895386575855550946571734371304009069495123321348655467 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 18216210481141884770383620344827254177059223714753710896012779494395740164436 | None | ||
| ate_bootstrap_disjoint | 16808166950809237583671512395223133458534143323315509068624130554453228182744 | None | ||
| chip_sw_rv_timer_systick_test | 84678656836422359112396954025489827181029107991760651905555998578955652931220 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 59633078298613118218199527479716355556357091868823095256438987802458719107728 | None | ||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 106274631625883230772183434732034407902931423762318961935046518458659531013462 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 99454437410123717041612810230390205316706131758083830806317663157390154356178 | None | ||
| ate_bootstrap_disjoint | 82863894710769028881949475646961608157258282886684077894027722509843884695279 | None | ||
| Offending '(rstreqs[*] && (reset_cause == HwReq))' | 10 test runs | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 34399639358609146856394121469255876016203003486004180731697209435429535072122 | 327 |
UVM_ERROR @ 10112.582500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10112.582500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 6725194909613580454365553971436143124748901385571761506530676324960144974214 | 319 |
UVM_ERROR @ 7586.066000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7586.066000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 84683672904091019280582536167363126265589194006887220354067313711396818239015 | 315 |
UVM_ERROR @ 5710.827000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5710.827000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 32810657195131743068186317550347029777254188375771320157523513471017455582488 | 314 |
UVM_ERROR @ 5173.552500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5173.552500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sysrst_ctrl_reset | 21879793249469485519001852205691259199187345402522560898345479287711142133180 | 334 |
UVM_ERROR @ 23529.936000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23529.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 65478663200041171905252810962797760784276462542952584920522294928678335084822 | 319 |
UVM_ERROR @ 7693.512000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7693.512000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 107379179886426931772056690423952997604077086834522478912202247323593954030070 | 315 |
UVM_ERROR @ 6080.734000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6080.734000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 2031684859551154815155061102199018696504694168328147854852036667016393644129 | 314 |
UVM_ERROR @ 5789.257000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5789.257000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 76413035855543686319096716475928734215623035440037327963649224858286656197277 | 325 |
UVM_ERROR @ 8389.920000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8389.920000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 11312111010620345092183039072065829415425184469222565967934391304922786260818 | 319 |
UVM_ERROR @ 7950.809000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7950.809000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 9 test runs | |||
| chip_sw_lc_walkthrough_dev | 107550118592420678322535877259941026561078324636927474480494465524588694584197 | 369 |
UVM_INFO @ 11243.993546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 104596560559701223834499397926141747190390525004703680535480601959206264224706 | 369 |
UVM_INFO @ 11582.503540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 9287484121095543381739453466403812877877074250717614216321239037020792102599 | 341 |
UVM_INFO @ 6894.889590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 78231955136149693240763011059956790100199144789936404512276354099180553290762 | 369 |
UVM_INFO @ 10498.052836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 8917797686064770229247710284632056527912097907004035310552133020153455113287 | 369 |
UVM_INFO @ 10689.687688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 70342711196345164175367454403918911379557893274323261562604742909487704477757 | 341 |
UVM_INFO @ 6593.136545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 80971449204128600355098258306957976471497180550779804256671369702051389857207 | 369 |
UVM_INFO @ 9455.684840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 80819316295658080979967792420604636832183522205379997263986193491051331716123 | 369 |
UVM_INFO @ 10900.860256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 25886062100503798707475475722014408133679778636595281571169447564919371365736 | 341 |
UVM_INFO @ 6715.158496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[NOA] Null object access | 7 test runs | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 57467658879830369546378364795124516559452882565943001771647282117771280161450 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_rma | 95807487394304812402949358849424119284569348335549052808992878085542021141626 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 82646625922050056966020961696494309374826008078198910864894864286435280854485 | 303 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_dev | 96146468697404912104579070762062700791263068512209037485474774471570237235455 | 303 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_rma | 3266934969815623454391082503147592552138379094199676716148292887597735861323 | 303 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 107891967923934817863725283481276836713516217201632896390191493383298879382861 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 13038154753624217655993594071998904785982278774656980676992162282173577338202 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' | 6 test runs | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 48460834063550566931997140311249171772401868229759264184651001783029184779867 | 313 |
UVM_ERROR @ 3227.901048 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3227.901048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 55651305508495770066135239835298606075982219321389917786807369098969448209826 | 451 |
UVM_ERROR @ 28760.305557 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 28760.305557 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 64888143891617878539125761623747792845032761350718984263441756416640077223684 | 313 |
UVM_ERROR @ 3549.988750 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3549.988750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 75329977608731809367450399061860482139611627437919672120846549351721310634647 | 368 |
UVM_ERROR @ 15203.784603 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 15203.784603 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 32151865630256788309900760226085830268040902359082162286918196987591161746711 | 313 |
UVM_ERROR @ 3381.053640 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3381.053640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 54505316236483492174024857388385666594454382022362519599671551258031047595911 | 405 |
UVM_ERROR @ 21785.662908 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 21785.662908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns | 6 test runs | |||
| chip_sw_hmac_multistream | 104920580535189172900783853549058836625581137760486162504761215030210593845990 | 340 |
UVM_INFO @ 12018.544414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_sideload_otbn | 18798760701983975563461553335387767064811936702103077550919370038045428100699 | 336 |
UVM_INFO @ 20026.497353 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_multistream | 112284228643239863188277599499478168439024789593871416113096569006418118456362 | 354 |
UVM_INFO @ 12026.834030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_sideload_otbn | 54014849592392482938135987808866352820087075407206984519817185122013513790431 | 334 |
UVM_INFO @ 20018.724999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_multistream | 58023788903080520019550041647293613096375151867683417208669581450239814202663 | 353 |
UVM_INFO @ 12026.701180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_keymgr_sideload_otbn | 62737179136891879261341620634370472116350656806038394932503988814285999133536 | 336 |
UVM_INFO @ 20018.600159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 6 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 83501336365009464728810879667103276048005840402689406960598418012169989154457 | 366 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 45102156116411748195486552981086907566464612481434425044764448995452723340208 | 368 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 89488491344824441735518216209818647024969670831573801816804771393425727013286 | 367 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 20955056249527744974468121745124085336868131415452990079645872806541132991994 | 325 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 101657542133999704123417662907162894258745284777963174500002441529123972612181 | 328 |
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 20173999651519293398287858202618869634591800441495320543952966765869888744641 | 328 |
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 4 test runs | |||
| chip_sw_otp_ctrl_escalation | 82212523853744474315933500351839910416593619234088814282555337603657175344062 | 316 |
UVM_ERROR @ 3235.053112 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3235.053112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 87829335423296845679845399207519911911365947665308339417858559764777241225838 | 312 |
UVM_ERROR @ 2673.915616 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2673.915616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 27915732962357387997228914018210409994931219549848296463912915628701872640582 | 312 |
UVM_ERROR @ 3331.368408 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3331.368408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 11655495500302525342092065506938636550732567674812610647771727712582018698298 | 317 |
UVM_ERROR @ 3777.792864 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3777.792864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path | 3 test runs | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 47174553569207762676332116578303165961796220654852566396865459478628337297786 | 301 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 2309442896653383495201545897382066833014971680823606864610808013444204692169 | 301 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 51696149206806507567360575449988284480537077944447648195455383384270127284202 | 301 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 3 test runs | |||
| chip_sw_spi_device_pass_through_collision | 71476095842753173249525075711426328403988371459632075838676443250330200587026 | 327 |
UVM_INFO @ 3320.347558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 113945968665485477243247826412221371881940527129877788816471675735251067400731 | 327 |
UVM_INFO @ 2777.777580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 113443171234256768473194224512339760746506770665556880396083617882527021169266 | 327 |
UVM_INFO @ 3012.909912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_flash_ctrl_lc_rw_en | 77573561721369596928850193332519901427553654061500500340982013340363565072526 | 309 |
UVM_INFO @ 3394.976150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 114285664071735201699842651272332498739366830775351108263353570231086292527092 | 309 |
UVM_INFO @ 3388.547864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 8471612525156526844473519204694363179696965706906637809447601669330967651042 | 309 |
UVM_INFO @ 3229.382800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * | 3 test runs | |||
| chip_sw_otp_ctrl_lc_signals_rma | 96914308622050376775510048620487669854965452324558626420482687769030096348955 | 342 |
UVM_INFO @ 8502.236873 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 68378361772796803793773692141483594309706313282668119646929752932906547793864 | 342 |
UVM_INFO @ 7012.091944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 36535406208848332813496914229063016540427167613803219293215092961201491562532 | 342 |
UVM_INFO @ 7503.632032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 3 test runs | |||
| chip_sw_pwrmgr_full_aon_reset | 34851038971576056504155303763253454465973561888792933899056643211669844013659 | 303 |
UVM_ERROR @ 2481.069537 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2481.069537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 63034075047867684723648741239625930170373835497379795889850529962572587594036 | 318 |
UVM_ERROR @ 6140.068928 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6140.068928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 100449838353971518202122907269501493331485259376256282416989792413288129326310 | 303 |
UVM_ERROR @ 2428.382888 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2428.382888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_clkmgr_jitter_frequency | 72880953243534031640815086987876798567154650535130450494993139879881327496924 | 343 |
UVM_INFO @ 3812.961260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 98577323678033407975970000397022258566149683772977840141108672733543014701436 | 343 |
UVM_INFO @ 4205.713830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 52566025269537694782519748512889075487841593088591659139632694294733784113911 | 343 |
UVM_INFO @ 4400.200855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. | 3 test runs | |||
| chip_sw_rv_dm_access_after_wakeup | 84381884662171734128738080547579727367376682424987303962196552306309979069777 | 329 |
UVM_INFO @ 13782.394736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rv_dm_access_after_wakeup | 39868013753969863398750456676530022552457501619497219817197960585516909079486 | 329 |
UVM_INFO @ 13094.681825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rv_dm_access_after_wakeup | 22256451031620045372545368627174359104319700687684991809055701070227472849722 | 329 |
UVM_INFO @ 13484.491286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) | 3 test runs | |||
| chip_sw_power_idle_load | 53969388451076261085175199390906907939633376040727132524201135770132370778302 | 318 |
UVM_INFO @ 15046.803048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 99703491952573746150803010943748869303998634865380071548141283665171319662395 | 318 |
UVM_INFO @ 14249.299102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 33114952759893844235916605966095902924958841912242705963267307375839686387978 | 318 |
UVM_INFO @ 14385.005162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) | 3 test runs | |||
| chip_sw_power_sleep_load | 44461646724023591675788290536097542962327330048236328984523787454287706497324 | 329 |
UVM_INFO @ 14849.303960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 8893421080363479503169963610331982628073410460403147355879279273569282465282 | 329 |
UVM_INFO @ 14800.663176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 114699303327461801885336441663926349160918794134958470791445792386649286029819 | 337 |
UVM_INFO @ 14946.421396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * | 3 test runs | |||
| chip_sw_ast_clk_rst_inputs | 109631930162276119689913816460631946030968206217113112381423410634532159262077 | 327 |
UVM_INFO @ 12900.614510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 79143500596781869242720320706234789330856334890798391115924834714732852268447 | 327 |
UVM_INFO @ 13827.170528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 109589616820195097167100065321402364757901898764313217876006505065291159989710 | 327 |
UVM_INFO @ 11145.696473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) | 3 test runs | |||
| ate_bootstrap_flash_erase | 66736190628088141677340728056895147453852816265560067985261612148839434739067 | 272 |
UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 76750262378055190617596799901853335599294653033743618824066093153163943398117 | 272 |
UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 17531429988286601706657069293868458750158284109254072734137309468109130031178 | 272 |
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* | 3 test runs | |||
| rom_e2e_shutdown_exception_c | 95921909857280878042603572468029965894800094802922752314535142747690854850534 | 319 |
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 4863.002217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_shutdown_exception_c | 86609825936516738201451219372941025355526634582032968286368481947119451887815 | 319 |
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 5523.905721 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_shutdown_exception_c | 103671470438146961656450439932916966571039459305733905736768656344045723799549 | 319 |
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 8006.095449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* | 3 test runs | |||
| rom_e2e_shutdown_output | 32032076703278062634898786978591953957077537014862868361558743401539639248768 | 312 |
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 7853.274870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_shutdown_output | 23978523786659139953652913578798170597310479985894580533585345451799610829396 | 312 |
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 6943.604777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_shutdown_output | 55950334426009773226615132176003363705206056791369902159909756302859591008058 | 312 |
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 9527.589689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 3 test runs | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 94081489949013674866666590642337216652910232419029018187416978909759757609767 | 328 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 58801028971324164112149408877670654482722330419730202696453406189632054600807 | 325 |
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 97429758607607866833917875904210387337547050773033405801995791121235408402544 | 326 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '$stable(key_data_i)' | 3 test runs | |||
| rom_keymgr_functest | 2551486116260666096360571635877358189163695577192943712055411078912576213495 | 327 |
UVM_ERROR @ 5366.219868 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5366.219868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 40262284957660257341009327294170288813310857738395658741548695331571920680492 | 327 |
UVM_ERROR @ 5228.713654 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5228.713654 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 58994948167874607540995267333245529561313039176794854433522640884312271493114 | 327 |
UVM_ERROR @ 4805.189751 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4805.189751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. | 3 test runs | |||
| chip_sw_all_escalation_resets | 46719429097574383951931453239800669421508245686206278716410658202448867447067 | 316 |
UVM_INFO @ 3032.759856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 88645758817308466777621953711034656334796438234668230446761667104253069703665 | 316 |
UVM_INFO @ 3146.345560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 99514579280416290739712509515140996920871901138870153046603459005702594023479 | 316 |
UVM_INFO @ 3513.047272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *! | 2 test runs | |||
| chip_sw_alert_test | 25859875375565069695154312888685373797274791788657416413956052184823261902275 | 307 |
UVM_INFO @ 2830.318565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_test | 47686285653758154935183504781019935530946465366822227952649356384667476451853 | 307 |
UVM_INFO @ 3297.939737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 34141953722649849234793339798317475678530372204822198945494264669811729303293 | 363 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 107582353100969014899625513496486425279514496796538547890640675546882410699964 | 325 |
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 47062659060786911861609183734382634721538394524716307540393748731140470272662 | 368 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 58312953130678547420547630151179704079525909041843146261357035802207387855251 | 328 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 2 test runs | |||
| chip_rv_dm_lc_disabled | 25958504609235541043478145827022281553745993042020235215403760041751044363526 | 247 |
UVM_INFO @ 7620.357913 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 58837983983504762263954752365164506692917018462761059547493143786149813490139 | 225 |
UVM_INFO @ 3897.750135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] | 1 test run | |||
| chip_sw_sleep_pin_mio_dio_val | 109477883483737982985193861318602093031710586344699456508558779098989527740883 | 451 |
UVM_INFO @ 3154.353000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_otp_ctrl_rot_auth_config | 59501512266438630961301180405117963207917383882073439042732061167485596625005 | 282 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_walkthrough_testunlocks | 108419173470565076103747969073619309326070830991512919104986156290597073172068 | 497 |
UVM_INFO @ 49634.603069 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 113612832298434111345135989455955091508060589819597969525391667552513912352947 | 325 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 12504674570648133365623988372358859413645593920148722106379773731922915555610 | 328 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) | 1 test run | |||
| rom_e2e_jtag_debug_test_unlocked0 | 16908511716629111393533209235650009625298693451134847041294394978988623430320 | 317 |
UVM_INFO @ 4263.855756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! | 1 test run | |||
| rom_e2e_jtag_debug_dev | 111841960089328937752483682844882660374928630811770543683689884799121892832459 | 330 |
UVM_INFO @ 13834.845590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * | 1 test run | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 88813244341309664284585157000246554174419445603382367314844412059587109824423 | 316 |
UVM_INFO @ 5707.478219 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 1 test run | |||
| rom_e2e_keymgr_init_rom_ext_no_meas | 36715155636815745173389735502714772123297661113907846643948060814080416102718 | 319 |
UVM_INFO @ 18387.021276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_walkthrough_prodend | 58371183554314862296510600781415858965766649215472358013901731428054759782070 | 308 |
UVM_INFO @ 26349.700363 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:357)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 110989825316173242158467987618373781006576230888079090734090515010563097830037 | 307 |
UVM_INFO @ 2985.292172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 1 test run | |||
| rom_e2e_keymgr_init_rom_ext_meas | 56594737663458886645006624113792392041053005589640601113416489245279576706862 | 319 |
UVM_INFO @ 15116.372500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got * | 1 test run | |||
| chip_sw_all_escalation_resets | 85215280168819392380741939194304808859137442406279547047900803737316273828465 | 317 |
UVM_INFO @ 3191.152565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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