Simulation Results

Simulation Results: clkmgr

11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
93.87 %

code
98.53 %

assert
95.76 %

func
87.31 %

line
99.07 %

branch
98.74 %

cond
95.64 %

toggle
99.19 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		70.34%
V3		100.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.610s	399.857us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.120s	25.436us	1	1	100.00
csr_rw				5	5	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
csr_bit_bash				1	1	100.00
	clkmgr_csr_bit_bash	7.720s	444.719us	1	1	100.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.880s	96.784us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	clkmgr_csr_mem_rw_with_rand_reset	2.630s	333.068us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
	clkmgr_csr_aliasing	1.880s	96.784us	1	1	100.00

127/127 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.260s	52.818us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	1.800s	134.586us	10	10	100.00
extclk				10	10	100.00
	clkmgr_extclk	2.340s	345.690us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.300s	109.640us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.610s	399.857us	10	10	100.00
frequency				10	10	100.00
	clkmgr_frequency	11.400s	2242.315us	10	10	100.00
frequency_timeout				10	10	100.00
	clkmgr_frequency_timeout	12.820s	2420.182us	10	10	100.00
frequency_overflow				10	10	100.00
	clkmgr_frequency	11.400s	2242.315us	10	10	100.00
stress_all				10	10	100.00
	clkmgr_stress_all	59.660s	10546.268us	10	10	100.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.270s	69.516us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	4.980s	524.058us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	4.980s	524.058us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	clkmgr_csr_hw_reset	1.120s	25.436us	1	1	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
	clkmgr_csr_aliasing	1.880s	96.784us	1	1	100.00
	clkmgr_same_csr_outstanding	2.170s	216.851us	5	5	100.00
tl_d_partial_access				12	12	100.00
	clkmgr_csr_hw_reset	1.120s	25.436us	1	1	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
	clkmgr_csr_aliasing	1.880s	96.784us	1	1	100.00
	clkmgr_same_csr_outstanding	2.170s	216.851us	5	5	100.00

V2S

102/145 passed

70.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				11	30	36.67
	clkmgr_sec_cm	72.780s	10005.178us	0	5	0.00
	clkmgr_tl_intg_err	70.730s	10011.395us	11	25	44.00
shadow_reg_update_error				9	20	45.00
	clkmgr_shadow_reg_errors	1045.950s	200000.000us	9	20	45.00
shadow_reg_read_clear_staged_value				9	20	45.00
	clkmgr_shadow_reg_errors	1045.950s	200000.000us	9	20	45.00
shadow_reg_storage_error				9	20	45.00
	clkmgr_shadow_reg_errors	1045.950s	200000.000us	9	20	45.00
shadowed_reset_glitch				9	20	45.00
	clkmgr_shadow_reg_errors	1045.950s	200000.000us	9	20	45.00
shadow_reg_update_error_with_csr_rw				8	20	40.00
	clkmgr_shadow_reg_errors_with_csr_rw	927.960s	200000.000us	8	20	40.00
sec_cm_bus_integrity				11	25	44.00
	clkmgr_tl_intg_err	70.730s	10011.395us	11	25	44.00
sec_cm_meas_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency	11.400s	2242.315us	10	10	100.00
sec_cm_timeout_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency_timeout	12.820s	2420.182us	10	10	100.00
sec_cm_meas_config_shadow				9	20	45.00
	clkmgr_shadow_reg_errors	1045.950s	200000.000us	9	20	45.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	1.580s	66.723us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				10	10	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.460s	113.587us	10	10	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.360s	77.356us	10	10	100.00
sec_cm_clk_handshake_intersig_mubi				9	10	90.00
	clkmgr_clk_handshake_intersig_mubi	1.500s	84.620us	9	10	90.00
sec_cm_div_intersig_mubi				10	10	100.00
	clkmgr_div_intersig_mubi	1.410s	57.045us	10	10	100.00
sec_cm_jitter_config_mubi				5	5	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	72.780s	10005.178us	0	5	0.00
sec_cm_meas_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
sec_cm_clk_ctrl_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.230s	25.708us	5	5	100.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	72.780s	10005.178us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				10	10	100.00
	clkmgr_regwen	6.040s	1115.968us	10	10	100.00
stress_all_with_rand_reset				10	10	100.00
	clkmgr_stress_all_with_rand_reset	179.780s	51499.089us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				16 test runs
	clkmgr_tl_intg_err	63281519161526676802065268329544490235990933896471359836194769312715397087414	129	UVM_INFO @ 10079569768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	48795720502718864664579306448657322557449935011966006532841118007388187844777	197	UVM_INFO @ 10127162951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	82687700109776974334232709406108564681388515420749050794160850615242306602559	79	UVM_INFO @ 10005177800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	109651219653888248036234740378645429438691011387002936773447231532523676555026	145	UVM_INFO @ 10067789932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	68474771458039567205612657348613333623163818610243669017084407233271682994330	124	UVM_INFO @ 10046114032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	54553521696456936448830368430456009532209124789335128460670394817985167764865	145	UVM_INFO @ 10061399723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	103877935085763556418557236753607479939719559332485167620297045754964571829888	89	UVM_INFO @ 10018305927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10536993724021417462240137991038618683990317265929432772649579397315882213223	136	UVM_INFO @ 10092908074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	73956771794067502709422083321800753824206809390065210415981214630006261945825	172	UVM_INFO @ 10092258922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	27707353008897942586074658537325863536117221623258726352714436636987184842906	147	UVM_INFO @ 10180530981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50604014145294444835919399174353802397357494918112458013522475130168647285986	123	UVM_INFO @ 10150658958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	44853405836278935322996192172056786229873441222310694749715820099443114265039	104	UVM_INFO @ 10011395044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	1182239226618122672871565880255140437769316858813379500918531681887223102489	154	UVM_INFO @ 10063530985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	76479283726589218977147130538228366213317422018596298896600756746536172022923	146	UVM_INFO @ 10049246155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	80133837280314317710555258410588310635797562999906078641992798409301444705131	101	UVM_INFO @ 10021935822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10155264277331752230097516800863374900335624698818847036298001554771078388613	229	UVM_INFO @ 10096559754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				15 test runs
	clkmgr_shadow_reg_errors	29781390832764991347561286079832810039042359560484205155692532010414146924584	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	2076940736302619827331839021549380519767225210585194468999067775943577543527	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	53311354974631075115077104614886858731766141080534286591285489832283205312633	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	13184941760652616434877371269476577940109561336467280242188147626700716215735	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	96162308398433199723752469992670350198525501149044228175976041177989028210169	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	9622456157961735061395965719944330597208029341989161966328525929890445626963	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	82786550413023136765097389276454657448107669114153769568228692329831441606459	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	51677697935076945471587737061296651835452537111392189898816505236761367827759	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	81876936077247393668178051431625465996664219090718024325286759300945416754661	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	108425384313037816931906775026522400851387653739958182149008743654029063250631	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	38094640218754969692648168401604907942311786710646841904795375135585116445003	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	97827167648137092875857724005555364486338116674275449672292012470202068862238	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	70638417251019328073091705850879519809820145622129843652688776425941565119968	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	828994764581489391034288750585850007063757979574119644658285268301227181104	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	2933772589275259710378731098928493991368984920624315718891537425200814519058	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				3 test runs
	clkmgr_sec_cm	24304712010041014580894953460999346360240866617337706708561624421625744041028	91	UVM_INFO @ 15608541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	113035341885727345300817442138692479291193285455297132939405381335692915645806	85	UVM_INFO @ 13924013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	51020573928443536823123418927479754551799579002247994567583547606179334581988	143	UVM_INFO @ 122224145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				2 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	112323752768710121781436297096217918503272483536158569485243272037894662189351	76	UVM_INFO @ 55761566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	108516181183370602389066918172009042572852575554816187114023859637790755594642	75	UVM_INFO @ 53154814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*)				2 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	41944103000307658093711027009827943137450312898467553419334843258892882051605	75	UVM_INFO @ 2114423842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	34280651383217297869889341225373441096809224390959324843776092884695629883064	76	UVM_INFO @ 2099411199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch				1 test run
	clkmgr_clk_handshake_intersig_mubi	10603245855590875174238634322854556510194385110122807980256302214960556082682	74	UVM_INFO @ 8468132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	25598442932605767672643174006013541617506975190499328885864366719259371396595	75	UVM_INFO @ 2077772271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	113226314078535315069153194119116600923361695541364627799767291229103154143969	75	UVM_INFO @ 2026151929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	27391134166761067605576368865898126047592547710695110392239290438137945534711	76	UVM_INFO @ 2388392038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	79848520677695851112809839689113857487899535942855568495888732349232700737784	76	UVM_INFO @ 2080084783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---