Simulation Results

Simulation Results: csrng

11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.69 %

code
96.17 %

assert
96.94 %

func
90.97 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.32%
V2S		98.60%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	6.000s	346.845us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	32.000s	60.222us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	31.000s	21.517us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	60.000s	661.750us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	32.000s	22.029us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	33.000s	38.295us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	31.000s	21.517us	5	5	100.00
	csrng_csr_aliasing	32.000s	22.029us	1	1	100.00

1285/1307 passed

98.32 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	69.000s	6886.715us	500	500	100.00
err				500	500	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
cmds				4	25	16.00
	csrng_cmds	339.000s	25645.380us	4	25	16.00
life cycle				4	25	16.00
	csrng_cmds	339.000s	25645.380us	4	25	16.00
stress_all				24	25	96.00
	csrng_stress_all	1376.000s	107800.675us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	25.000s	53.223us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	33.000s	41.086us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	13.000s	502.996us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	13.000s	502.996us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	32.000s	60.222us	1	1	100.00
	csrng_csr_rw	31.000s	21.517us	5	5	100.00
	csrng_csr_aliasing	32.000s	22.029us	1	1	100.00
	csrng_same_csr_outstanding	15.000s	84.437us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	32.000s	60.222us	1	1	100.00
	csrng_csr_rw	31.000s	21.517us	5	5	100.00
	csrng_csr_aliasing	32.000s	22.029us	1	1	100.00
	csrng_same_csr_outstanding	15.000s	84.437us	5	5	100.00

V2S

1267/1285 passed

98.60 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
	csrng_tl_intg_err	8.000s	159.345us	25	25	100.00
sec_cm_config_regwen				13	30	43.33
	csrng_regwen	18.000s	10.815us	8	25	32.00
	csrng_csr_rw	31.000s	21.517us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	69.000s	6886.715us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	1376.000s	107800.675us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	69.000s	6886.715us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	1376.000s	107800.675us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	69.000s	6886.715us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	8.000s	159.345us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00
	csrng_sec_cm	23.000s	317.560us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	31.000s	322.677us	200	200	100.00
	csrng_err	30.000s	27.147us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				18 test runs
	csrng_cmds	30367601252394331709885930439198631789556765711102686383584029764213926149430	120	UVM_INFO @ 767696054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	75568197296252200116603976109672097189804780371535744229948753841348574033276	100	UVM_INFO @ 88280726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	25925709839219743540278631064668694946230527287411864745387304728437020787795	100	UVM_INFO @ 86042888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	69775512331786745332645004248493520737846980004928418261745771011101273288212	100	UVM_INFO @ 21122267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	113072809326564362035171713484953478834669082086882971320972182955026399581824	110	UVM_INFO @ 108780277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	71222256473230621926212450112915178560121381660770148551390848480961052701824	100	UVM_INFO @ 100116458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108707214298166452227311431707687140925959988480312943638031455736103523470334	100	UVM_INFO @ 46865700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	62128708697060939661719507975690343607742628601682491715936130539237432144859	100	UVM_INFO @ 42561222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	63750696353281962111543301137743155356662776575559619682569680483983632802310	100	UVM_INFO @ 117308859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76648838185338438317176120868763440122686547857325557272820886548517228877450	100	UVM_INFO @ 286365232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	87792238677786577896377362725178690397531806431324538974011261692191742245714	100	UVM_INFO @ 183215011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18589523450565582541711965286659885223749260467461910419217937269638843532675	100	UVM_INFO @ 515753179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	14176189903243482181908623784042584516822559553429389843048589127087990613118	100	UVM_INFO @ 82840537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24658928218179258321696169428505863965035024572813114406133146563883005363815	100	UVM_INFO @ 58695226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6834569675016996295720074885254117332919643603351165658639072521795721547554	100	UVM_INFO @ 180264238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	13643047638068066857107545653431714385703795245387319432636611398781682284613	100	UVM_INFO @ 89999776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105114741183622692082997625438054246879672978301582788919241699841986904622539	100	UVM_INFO @ 254474082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	78868548895190587861253707110356973233437053982446429600137000840032555427301	100	UVM_INFO @ 210491807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				12 test runs
	csrng_regwen	41552952244870439715807878483939250522598737643120915363605549024231427190988	99	UVM_INFO @ 7024272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	19627294332465093096718026186536843753722122614623409582031456500043578729775	99	UVM_INFO @ 3049041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	65300030396921422231656044338751786924262959997703223677691502108389448105033	99	UVM_INFO @ 1292762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	71406972488310094712300404638440897281638480605840410189195680991677021691569	99	UVM_INFO @ 11218533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	17848253568240375909213215236531796443774137974008865585772046378694701612956	99	UVM_INFO @ 41801839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	99893235517735768229094058415282377046030687394189871229283391666335546990994	99	UVM_INFO @ 6367109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	106088605034876140595122010879620965358057179134096385853233188373407140309926	99	UVM_INFO @ 1978279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	85443087861942146073737751440360439011725926485910645109038643167848561538831	99	UVM_INFO @ 11664246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	66464375579099369211385438025485413566986796941720731167969457469263814249611	99	UVM_INFO @ 4676198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	18069735894141363222439631090882219744507524231459863005914059002924132859052	99	UVM_INFO @ 2664485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	21595943177847626934820279664734557092459823606509553539476569179532205473802	99	UVM_INFO @ 1628310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	109038761704662623772366790468090561610532386170463896722435621160691556620926	99	UVM_INFO @ 3654599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				8 test runs
	csrng_stress_all_with_rand_reset	93329762988289622349895985817352742436523070237758491434132120512900390729765	None
	csrng_stress_all_with_rand_reset	76643689940372747172570497121313957410423544448013546165550891053498510381280	None
	csrng_stress_all_with_rand_reset	101028712972694284731235179206243484246603227021630095297693700168505994953330	None
	csrng_stress_all_with_rand_reset	71303067009439067620512288434509765179498370833910040484133955666191327780577	None
	csrng_stress_all_with_rand_reset	45617202556562579350586124396958362269039887456189818946424906496364776715299	None
	csrng_stress_all_with_rand_reset	65467149189790214625075667696249774765093749515665390859187387745181538512528	None
	csrng_stress_all_with_rand_reset	106126176497331072024076688658884618275353933695526721696365410278088350554564	None
	csrng_stress_all_with_rand_reset	59395635014869029695303035152683592106806584954182008752020356245134776863871	None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				5 test runs
	csrng_regwen	114051257229986910202292210937654205407617986051257108187047687378412137454283	99	UVM_INFO @ 10815136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	57053468344509326736613173440016455742543206138165417171083302048443941829831	99	UVM_INFO @ 6029457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	104926394867183620339531865700006427866767641019629528281468397497009129104688	99	UVM_INFO @ 9838912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	50042102113439869803475909464923447998723660639951972443446101231604566739584	99	UVM_INFO @ 5100907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	38383373604200116203964858116237329925406585572734163554499686274390578546423	99	UVM_INFO @ 6486781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				2 test runs
	csrng_cmds	76806173761229200590363030545751072442239223177071310831164112316696733710403	109	UVM_INFO @ 506800626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	77638673527652397604200977683466921726733389585579552046185177640357224049500	119	UVM_INFO @ 226312590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	52823195553705569490365541555753303259549628410556110480053929446000471392541	153	UVM_INFO @ 3899772255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				1 test run
	csrng_stress_all_with_rand_reset	75695913986674254113443951503061311783556730859620953783550144117796627933350	175	UVM_INFO @ 1589928019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				1 test run
	csrng_stress_all	69392676563739094248967974245479565124728802735853389550741062956500975749914	108	UVM_INFO @ 3065443954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	33531036125458007798252790995172689178342179659913687569609331338356631072269	108	UVM_INFO @ 8950598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---