Simulation Results: edn/edn0

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 95.35 %
  • assert
  • 98.92 %
  • func
  • 92.66 %
  • line
  • 98.86 %
  • branch
  • 96.23 %
  • cond
  • 93.67 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.200s 18.566us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.270s 28.590us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.200s 36.743us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.510s 340.368us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.510s 38.356us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.770s 86.329us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.200s 36.743us 5 5 100.00
edn_csr_aliasing 1.510s 38.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.590s 828.551us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.590s 828.551us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.590s 828.551us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.340s 29.508us 20 20 100.00
alerts 200 200 100.00
edn_alert 2.030s 275.148us 200 200 100.00
errs 100 100 100.00
edn_err 1.930s 29.019us 100 100 100.00
disable 92 100 92.00
edn_disable 1.310s 14.301us 50 50 100.00
edn_disable_auto_req_mode 4.140s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 6.310s 279.907us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.320s 16.568us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.310s 118.230us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.760s 152.046us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.760s 152.046us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.270s 28.590us 1 1 100.00
edn_csr_rw 1.200s 36.743us 5 5 100.00
edn_csr_aliasing 1.510s 38.356us 1 1 100.00
edn_same_csr_outstanding 1.330s 60.807us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.270s 28.590us 1 1 100.00
edn_csr_rw 1.200s 36.743us 5 5 100.00
edn_csr_aliasing 1.510s 38.356us 1 1 100.00
edn_same_csr_outstanding 1.330s 60.807us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 11.040s 1205.369us 5 5 100.00
edn_tl_intg_err 2.480s 555.438us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.360s 32.147us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 2.030s 275.148us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.040s 1205.369us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.040s 1205.369us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.040s 1205.369us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.040s 1205.369us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 2.030s 275.148us 200 200 100.00
edn_sec_cm 11.040s 1205.369us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 2.030s 275.148us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.480s 555.438us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 76.610s 8055.212us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 6 test runs
edn_disable_auto_req_mode 58040254326546286948787706333911385112706480376780815543332909643011117532152 88
UVM_INFO @ 47827452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 13585326697206829699373563214483621784728433511976154896068705575584606189478 88
UVM_INFO @ 23987054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 18656922687526249465301361001737368565966771060700489166375273184328660362087 88
UVM_INFO @ 18967522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 96009223098110545987748054450631617617456758867000981520310879217715005730054 88
UVM_INFO @ 45648124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 102316684580729311510482904191587783475106043853693471907664497532956388566500 88
UVM_INFO @ 33286891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 49347720820825806395310832637704944087438399509908687584593509987763830716292 88
UVM_INFO @ 34319929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 30301338706686358332225842914027739599675037555806228165277165962836356203521 273
UVM_INFO @ 2581238426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 1602755632678128289172439856806699108598114532485066386288776828589392851085 147
UVM_INFO @ 414130103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 97434706414677672771971857893982129870097758156689852997292482659935260399375 277
UVM_INFO @ 3437916118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 9148472690835024659959144270076441827710802066833378539546857071072773278878 149
UVM_INFO @ 672721821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 35817495446125219277803544345134751408689816323123542265855534441083320394825 153
UVM_INFO @ 1441045048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
edn_disable_auto_req_mode 103088036804790415725090734819795860589929592512135421883843754701962721527661 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62545842717508036382756955717011959742553977603173779821856199378751619496020 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---