Simulation Results: edn/edn1

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 95.89 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.19%
V2S
100.00%
V3
76.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.030s 32.438us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 72.872us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 0.930s 41.494us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.020s 321.301us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.980s 28.311us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.510s 77.702us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 0.930s 41.494us 5 5 100.00
edn_csr_aliasing 0.980s 28.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.140s 679.264us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.140s 679.264us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.140s 679.264us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.060s 20.909us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.650s 30.423us 200 200 100.00
errs 100 100 100.00
edn_err 1.660s 63.177us 100 100 100.00
disable 89 100 89.00
edn_disable 1.270s 16.035us 50 50 100.00
edn_disable_auto_req_mode 2.270s 500.000us 39 50 78.00
stress_all 30 30 100.00
edn_stress_all 9.240s 577.244us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.100s 31.084us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.100s 76.125us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.170s 249.910us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.170s 249.910us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.880s 72.872us 1 1 100.00
edn_csr_rw 0.930s 41.494us 5 5 100.00
edn_csr_aliasing 0.980s 28.311us 1 1 100.00
edn_same_csr_outstanding 1.290s 35.829us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.880s 72.872us 1 1 100.00
edn_csr_rw 0.930s 41.494us 5 5 100.00
edn_csr_aliasing 0.980s 28.311us 1 1 100.00
edn_same_csr_outstanding 1.290s 35.829us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.080s 636.610us 5 5 100.00
edn_tl_intg_err 3.500s 192.415us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.090s 19.761us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.650s 30.423us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.080s 636.610us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.080s 636.610us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.080s 636.610us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.080s 636.610us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.650s 30.423us 200 200 100.00
edn_sec_cm 4.080s 636.610us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.650s 30.423us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.500s 192.415us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 30 76.67
edn_stress_all_with_rand_reset 69.500s 16290.538us 23 30 76.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 8 test runs
edn_disable_auto_req_mode 42686937382308223935781366001752521782001379269139400393280644034984286061470 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88204410218274168928941886022052282939331251547555788565257919619757609501377 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 113976863329177743678603684505299019504359207892890083191713272291168984676267 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 9713817928479923718940723813553959266842673845682442043630634832800640620668 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 74908435393551484852626792432939776814471754889514890310547224676292636474451 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34017178558456768793072138877474844316589289834338424993864380590930600318493 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 104020249351268478203563824468731182805678748097770059037245018558711948761907 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 110239389160052216201450458968193253005018331189992335440856336842849479063690 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 7774769861267332743847418882838776480921062852206369871957728668418950543301 309
UVM_INFO @ 4099920123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 82064718760513997282344800612327144943926041883371023208108292671368745620311 152
UVM_INFO @ 561103635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 5525415562201779656830379936085549845331646933590599506525544122077239309721 197
UVM_INFO @ 2087400748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 71184472330616165687796585262652570021130068529166381333252863904284530763388 131
UVM_INFO @ 365646451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 55128171400031287773504723670749057058160725751922250276917310369521931345847 149
UVM_INFO @ 1214912584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 8000797468981382014434335324411549237056836432067975375848065403729957501573 138
UVM_INFO @ 1205879224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 30667403149939474201501835904380314461921218170958935113223401283816250603785 256
UVM_INFO @ 1017655404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 18308444185083398561120879291022012103616054006317223076701506625641346369165 88
UVM_INFO @ 26208732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11080122609088918119219331260434289170958153992124934958329926973596227795645 88
UVM_INFO @ 28085904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 31211270011667882216624832334290663438311015521859257729152522829425749465808 88
UVM_INFO @ 30065246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---