Simulation Results: flash_ctrl

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.08 %
  • code
  • 95.78 %
  • assert
  • 97.02 %
  • func
  • 98.45 %
  • line
  • 96.10 %
  • branch
  • 97.42 %
  • cond
  • 94.88 %
  • toggle
  • 98.66 %
  • FSM
  • 91.84 %
Validation stages
V1
100.00%
V2
99.04%
V2S
98.95%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 154.340s 200.014us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 26.540s 33.992us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.540s 86.705us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 36.070s 1892.945us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 61.820s 5060.029us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 17.770s 57.488us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
flash_ctrl_csr_aliasing 61.820s 5060.029us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 11.040s 169.845us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 12.670s 75.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 25.290s 42.178us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 71.260s 52.075us 5 5 100.00
rma_hw_if 42 43 97.67
flash_ctrl_hw_rma 1484.210s 491052.288us 3 3 100.00
flash_ctrl_hw_rma_reset 671.070s 80143.897us 20 20 100.00
flash_ctrl_lcmgr_intg 14.670s 23.818us 19 20 95.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2131.490s 1300150.906us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 313.160s 6726.330us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 146.880s 3036.239us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3082.540s 970489.680us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 101.030s 1417.714us 5 5 100.00
rd_buff_eviction_w_ecc 103 105 98.10
flash_ctrl_rw_evict 34.190s 93.130us 39 40 97.50
flash_ctrl_rw_evict_all_en 32.610s 319.501us 39 40 97.50
flash_ctrl_re_evict 32.680s 324.747us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 192.850s 411.387us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 192.850s 411.387us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 584.360s 26372.770us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 32.630s 2776.753us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 576.030s 334.039us 20 20 100.00
error_mp 9 10 90.00
flash_ctrl_error_mp 621.050s 14294.362us 9 10 90.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 581.680s 2025.513us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1358.040s 1438.064us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 15.010s 77.630us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 154.590s 1580.430us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 24.230s 18.864us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 18.330s 25.160us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 1223.920s 605.843us 5 5 100.00
secret_partition 130 130 100.00
flash_ctrl_hw_sec_otp 159.790s 10535.006us 50 50 100.00
flash_ctrl_otp_reset 108.700s 670.239us 80 80 100.00
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1484.210s 491052.288us 3 3 100.00
interrupts 99 100 99.00
flash_ctrl_intr_rd 207.990s 9612.619us 39 40 97.50
flash_ctrl_intr_wr 82.840s 6518.041us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 401.230s 205440.237us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 316.510s 170336.392us 10 10 100.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 64.750s 4653.588us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 62.140s 1090.492us 5 5 100.00
double_bit_err 35 35 100.00
flash_ctrl_read_word_sweep_derr 20.270s 519.749us 5 5 100.00
flash_ctrl_ro_derr 119.270s 5807.184us 10 10 100.00
flash_ctrl_rw_derr 188.510s 2434.792us 10 10 100.00
flash_ctrl_derr_detect 135.670s 10103.367us 5 5 100.00
flash_ctrl_integrity 469.870s 9291.024us 5 5 100.00
single_bit_err 23 25 92.00
flash_ctrl_read_word_sweep_serr 23.070s 30.651us 5 5 100.00
flash_ctrl_ro_serr 131.710s 873.185us 10 10 100.00
flash_ctrl_rw_serr 3604.012s 0.000us 8 10 80.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 76.190s 2507.943us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 81.050s 6285.372us 5 5 100.00
scramble 60 62 96.77
flash_ctrl_wo 155.210s 14772.806us 20 20 100.00
flash_ctrl_write_word_sweep 14.860s 92.898us 1 1 100.00
flash_ctrl_read_word_sweep 13.870s 37.345us 1 1 100.00
flash_ctrl_ro 109.110s 967.557us 19 20 95.00
flash_ctrl_rw 3603.479s 0.000us 19 20 95.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 28.620s 409.907us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 702.520s 82373.255us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 241.840s 10020.404us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 13.850s 90.192us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 12.820s 24.009us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 20.080s 269.156us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 20.080s 269.156us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 16.540s 86.705us 1 1 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
flash_ctrl_csr_aliasing 61.820s 5060.029us 1 1 100.00
flash_ctrl_same_csr_outstanding 32.930s 298.233us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 16.540s 86.705us 1 1 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
flash_ctrl_csr_aliasing 61.820s 5060.029us 1 1 100.00
flash_ctrl_same_csr_outstanding 32.930s 298.233us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 88.640s 101.149us 20 20 100.00
tl_intg_err 29 30 96.67
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
flash_ctrl_tl_intg_err 645.480s 1173.100us 24 25 96.00
sec_cm_reg_bus_integrity 24 25 96.00
flash_ctrl_tl_intg_err 645.480s 1173.100us 24 25 96.00
sec_cm_host_bus_integrity 24 25 96.00
flash_ctrl_tl_intg_err 645.480s 1173.100us 24 25 96.00
sec_cm_mem_bus_integrity 5 6 83.33
flash_ctrl_rd_intg 31.720s 133.880us 3 3 100.00
flash_ctrl_wr_intg 15.020s 96.839us 2 3 66.67
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 154.340s 200.014us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 260 260 100.00
flash_ctrl_otp_reset 108.700s 670.239us 80 80 100.00
flash_ctrl_disable 24.230s 18.864us 50 50 100.00
flash_ctrl_sec_info_access 71.580s 11078.462us 50 50 100.00
flash_ctrl_connect 18.330s 25.160us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 14.540s 23.837us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 17.400s 29.416us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 59.180s 64.860us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 24.230s 18.864us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 31.720s 133.880us 3 3 100.00
flash_ctrl_access_after_disable 11.460s 22.413us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 25.980s 27.834us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 24.230s 18.864us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 32.630s 2776.753us 10 10 100.00
sec_cm_mem_scramble 19 20 95.00
flash_ctrl_rw 3603.479s 0.000us 19 20 95.00
sec_cm_mem_integrity 23 25 92.00
flash_ctrl_rw_serr 3604.012s 0.000us 8 10 80.00
flash_ctrl_rw_derr 188.510s 2434.792us 10 10 100.00
flash_ctrl_integrity 469.870s 9291.024us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1484.210s 491052.288us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 18.670s 875.396us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 5 5 100.00
flash_ctrl_phy_host_grant_err 13.910s 24.104us 5 5 100.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 15.540s 66.345us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2473.700s 1456.379us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 40.020s 920.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 432.140s 820.846us 3 3 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
flash_ctrl_rw_serr 18707868590186664672623310225666157806467232523752496422821192037635348222751 None
flash_ctrl_rw 100554829380686040368849329550710461036712887555324647580740933706379628459447 None
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [*] vs * [*]) 1 test run
flash_ctrl_error_mp 46224243194896353346619796034035802296101885349676676459699308480496115748788 369
UVM_INFO @ 1600271.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [wdata_page0_comp_bank1] *: obs:exp e046d4c3_3786be93:638c4401_f9a6e4f* mismatch!! 1 test run
flash_ctrl_wr_intg 94081965750913880917125648072181168351052402638810141251359095019210800997417 125
UVM_INFO @ 61769.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start 1 test run
flash_ctrl_lcmgr_intg 41020506837252256504481228698838834174049865358645730096421464404332054928895 108
UVM_INFO @ 500000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 1 test run
flash_ctrl_ro 58983365081076843578559941959352202446114854398779803219678759281337788074381 108
UVM_INFO @ 258730.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_rw_serr 60947994679613662284051789888877103922068153717658202084887086199376347562863 108
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{*:*} 1 test run
flash_ctrl_tl_intg_err 20037558646554405496151137155299021557308841088587603178676823398897022745787 308
UVM_INFO @ 792255.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 1 test run
flash_ctrl_rw_evict_all_en 100986266560624873049826769758700444095176257696834460947965883306945372680336 108
UVM_INFO @ 22160.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *f3_f9d3667d:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 87029447735654809627291044133766941450891694210905088879134851447050552848816 108
UVM_INFO @ 1450627.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * 1 test run
flash_ctrl_rw_evict 67803670814542478028811155900878626487323182922682901348651130835140360420010 108
UVM_INFO @ 220408.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---