Simulation Results: gpio

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.96 %
  • code
  • 98.14 %
  • assert
  • 98.73 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 93.43 %
Validation stages
V1
100.00%
V2
94.90%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.860s 243.456us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.560s 337.061us 10 10 100.00
gpio_smoke_en_cdc_prim 1.870s 111.378us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.980s 396.764us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 1.000s 76.411us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.970s 30.231us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 1.860s 148.530us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.180s 64.013us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.970s 67.000us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.970s 30.231us 5 5 100.00
gpio_csr_aliasing 1.180s 64.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.860s 89.015us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.470s 90.187us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.300s 55.480us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.750s 104.386us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 3.160s 148.524us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.130s 294.813us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 31.130s 556.134us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 4.430s 3127.448us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.380s 82.485us 10 10 100.00
stress_all 2 10 20.00
gpio_stress_all 112.100s 22868.167us 2 10 20.00
alert_test 10 10 100.00
gpio_alert_test 0.930s 27.675us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.990s 14.256us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 3.520s 177.517us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 3.520s 177.517us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.970s 30.231us 5 5 100.00
gpio_same_csr_outstanding 1.290s 47.137us 5 5 100.00
gpio_csr_aliasing 1.180s 64.013us 1 1 100.00
gpio_csr_hw_reset 1.000s 76.411us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.970s 30.231us 5 5 100.00
gpio_same_csr_outstanding 1.290s 47.137us 5 5 100.00
gpio_csr_aliasing 1.180s 64.013us 1 1 100.00
gpio_csr_hw_reset 1.000s 76.411us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.920s 844.820us 25 25 100.00
gpio_sec_cm 1.220s 256.960us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.920s 844.820us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 10 10 100.00
gpio_rand_straps 0.950s 45.017us 10 10 100.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 11.130s 971.018us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 8 test runs
gpio_stress_all 2860646483955410906007793947041126575646183004121923607088753821351765688023 3935
UVM_INFO @ 22868167341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 42162654060662365817037603425199847709431844154463085898881778728629307031839 76
UVM_INFO @ 30723071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 31294730703736808962024688657727930277820875289528720518701152119037999604174 75
UVM_INFO @ 5881764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 93809639490216813143531260728509047047135749160812565247304232188321685626706 76
UVM_INFO @ 2373664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 41408205647231569684590523942761134293588884962464891973339692461208264394932 75
UVM_INFO @ 8121964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 20358210021883597604878390704705768590563975123083509057082365007314532522373 550
UVM_INFO @ 1507549389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 54194193228770321566909984952164710014760486893041399784865481232274105633483 721
UVM_INFO @ 6202952154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 111132220186913851648744846666924637197771214816435005632015717144852648161101 80
UVM_INFO @ 1337501994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 6 test runs
gpio_stress_all_with_rand_reset 71061024971655970936894359259074751101254216960803203393524763352594494572707 78
UVM_INFO @ 3674737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 3210395944566375881342074600429304601410250425292876291125608032953041320114 188
UVM_INFO @ 971017632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 40914601167589184131502243918776378429594241890460013910614081222185941718560 238
UVM_INFO @ 147743403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 96911994316488139212518395588801480672827601397647779144433583312080226873740 79
UVM_INFO @ 217056251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91608469064272270532107276455661289732596636157771773739756102339082268312779 78
UVM_INFO @ 66528317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85687352301924350986587721918601669579772545636977717320925756541014145914655 78
UVM_INFO @ 28895280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 4 test runs
gpio_stress_all_with_rand_reset 53828481551745622601319471542683889466117637768102237792085252038518022105960 80
UVM_INFO @ 71832207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 43807598223946134412869919400832391023174936454530530492749493808200954884732 81
UVM_INFO @ 106906928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 75846484554795546554868525325543545194308973703578036077371743706296800473612 192
UVM_INFO @ 543046730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 96108479667912293591811192851523137799975125155865689545106631618615448669372 80
UVM_INFO @ 6545302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---