Simulation Results: hmac

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.20 %
  • assert
  • 97.60 %
  • func
  • 99.79 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.150s 736.140us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.050s 72.464us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.210s 81.068us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.800s 571.191us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.480s 375.153us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 408.190s 77608.309us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.210s 81.068us 5 5 100.00
hmac_csr_aliasing 6.480s 375.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 63.420s 63317.113us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 110.210s 9652.254us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 276.530s 45022.444us 30 30 100.00
hmac_test_sha384_vectors 526.890s 42117.929us 75 75 100.00
hmac_test_sha512_vectors 553.020s 41710.318us 75 75 100.00
hmac_test_hmac256_vectors 15.810s 496.122us 50 50 100.00
hmac_test_hmac384_vectors 17.470s 468.059us 60 60 100.00
hmac_test_hmac512_vectors 19.130s 1583.025us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 35.370s 7042.772us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1353.610s 10958.170us 10 10 100.00
error 10 10 100.00
hmac_error 122.810s 50204.373us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 111.620s 12608.355us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.150s 736.140us 10 10 100.00
hmac_long_msg 63.420s 63317.113us 10 10 100.00
hmac_back_pressure 110.210s 9652.254us 25 25 100.00
hmac_datapath_stress 1353.610s 10958.170us 10 10 100.00
hmac_burst_wr 35.370s 7042.772us 50 50 100.00
hmac_stress_all 3212.320s 40316.659us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.150s 736.140us 10 10 100.00
hmac_long_msg 63.420s 63317.113us 10 10 100.00
hmac_back_pressure 110.210s 9652.254us 25 25 100.00
hmac_datapath_stress 1353.610s 10958.170us 10 10 100.00
hmac_wipe_secret 111.620s 12608.355us 10 10 100.00
hmac_test_sha256_vectors 276.530s 45022.444us 30 30 100.00
hmac_test_sha384_vectors 526.890s 42117.929us 75 75 100.00
hmac_test_sha512_vectors 553.020s 41710.318us 75 75 100.00
hmac_test_hmac256_vectors 15.810s 496.122us 50 50 100.00
hmac_test_hmac384_vectors 17.470s 468.059us 60 60 100.00
hmac_test_hmac512_vectors 19.130s 1583.025us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.150s 736.140us 10 10 100.00
hmac_long_msg 63.420s 63317.113us 10 10 100.00
hmac_back_pressure 110.210s 9652.254us 25 25 100.00
hmac_datapath_stress 1353.610s 10958.170us 10 10 100.00
hmac_burst_wr 35.370s 7042.772us 50 50 100.00
hmac_error 122.810s 50204.373us 10 10 100.00
hmac_wipe_secret 111.620s 12608.355us 10 10 100.00
hmac_test_sha256_vectors 276.530s 45022.444us 30 30 100.00
hmac_test_sha384_vectors 526.890s 42117.929us 75 75 100.00
hmac_test_sha512_vectors 553.020s 41710.318us 75 75 100.00
hmac_test_hmac256_vectors 15.810s 496.122us 50 50 100.00
hmac_test_hmac384_vectors 17.470s 468.059us 60 60 100.00
hmac_test_hmac512_vectors 19.130s 1583.025us 75 75 100.00
hmac_stress_all 3212.320s 40316.659us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3212.320s 40316.659us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.940s 28.571us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.980s 66.917us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.010s 166.487us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.010s 166.487us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.050s 72.464us 1 1 100.00
hmac_csr_rw 1.210s 81.068us 5 5 100.00
hmac_csr_aliasing 6.480s 375.153us 1 1 100.00
hmac_same_csr_outstanding 2.870s 154.189us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.050s 72.464us 1 1 100.00
hmac_csr_rw 1.210s 81.068us 5 5 100.00
hmac_csr_aliasing 6.480s 375.153us 1 1 100.00
hmac_same_csr_outstanding 2.870s 154.189us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.380s 346.462us 5 5 100.00
hmac_tl_intg_err 4.870s 1051.208us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.870s 1051.208us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.150s 736.140us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.120s 470.403us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1023.270s 77331.135us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.910s 57.036us 1 1 100.00