Simulation Results: keymgr

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 98.79 %
  • assert
  • 97.72 %
  • func
  • 91.26 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.08 %
  • toggle
  • 97.68 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.77%
V2S
99.38%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 15.850s 2134.036us 30 30 100.00
random 30 30 100.00
keymgr_random 86.350s 10648.412us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.500s 88.097us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 18.770s 820.729us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 7.040s 694.152us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.870s 37.434us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
keymgr_csr_aliasing 7.040s 694.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 75.090s 4194.204us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 19.260s 2517.756us 20 20 100.00
keymgr_sideload_kmac 29.940s 5940.843us 20 20 100.00
keymgr_sideload_aes 28.380s 1480.420us 20 20 100.00
keymgr_sideload_otbn 14.900s 11418.817us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 25.190s 1678.572us 30 30 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 5.990s 543.888us 50 50 100.00
kmac_error_response 19 20 95.00
keymgr_kmac_rsp_err 6.330s 774.157us 19 20 95.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 12.560s 1492.352us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 25.790s 1158.979us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 9.440s 1844.360us 20 20 100.00
stress_all 50 50 100.00
keymgr_stress_all 794.340s 74157.066us 50 50 100.00
intr_test 10 10 100.00
keymgr_intr_test 1.190s 10.801us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.200s 33.325us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 4.540s 703.222us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 4.540s 703.222us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.500s 88.097us 1 1 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
keymgr_csr_aliasing 7.040s 694.152us 1 1 100.00
keymgr_same_csr_outstanding 3.320s 108.786us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.500s 88.097us 1 1 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
keymgr_csr_aliasing 7.040s 694.152us 1 1 100.00
keymgr_same_csr_outstanding 3.320s 108.786us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
keymgr_tl_intg_err 9.460s 3035.099us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.650s 172.287us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.650s 172.287us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.650s 172.287us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.650s 172.287us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.380s 3739.798us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 9.460s 3035.099us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.650s 172.287us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 75.090s 4194.204us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 86.350s 10648.412us 30 30 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 86.350s 10648.412us 30 30 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 86.350s 10648.412us 30 30 100.00
keymgr_csr_rw 1.830s 29.700us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 5.990s 543.888us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 25.790s 1158.979us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 25.790s 1158.979us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 86.350s 10648.412us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 13.670s 5995.394us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_ctrl_fsm_consistency 48 50 96.00
keymgr_custom_cm 14.120s 1065.413us 48 50 96.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 5.990s 543.888us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 48 50 96.00
keymgr_custom_cm 14.120s 1065.413us 48 50 96.00
sec_cm_kmac_if_done_ctrl_consistency 48 50 96.00
keymgr_custom_cm 14.120s 1065.413us 48 50 96.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 48 50 96.00
keymgr_custom_cm 14.120s 1065.413us 48 50 96.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.690s 2515.605us 5 5 100.00
sec_cm_ctrl_key_integrity 48 50 96.00
keymgr_custom_cm 14.120s 1065.413us 48 50 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 11 20 55.00
keymgr_stress_all_with_rand_reset 18.820s 2307.524us 11 20 55.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 9 test runs
keymgr_stress_all_with_rand_reset 28935614408184292590252810630294267779130642467801230223601955958897278178087 516
UVM_INFO @ 242197778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 11152862732110812927623158816498648417795037211316200355279872385030161516867 228
UVM_INFO @ 114994750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 30993871032696494467916029846236196497498442294080610552046213770947279999216 1078
UVM_INFO @ 2288976122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23807550878070207962121946582869599077338761960725410309709432045175338689417 325
UVM_INFO @ 334242858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 56794973761956653875851460222920115517336051892337382905743159383019778050839 615
UVM_INFO @ 735067775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 1892928400898618200218453780041950976177954376533398143943767441356166787716 326
UVM_INFO @ 472079648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79029129878608406883993814194482721730111993389362167907995420169654619139527 181
UVM_INFO @ 122900513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 107727852887141701767956108817617203021030607919647314864729245741854374071649 528
UVM_INFO @ 966907803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18827855202610128467509263274767179975382029951467608021613103311297854114472 267
UVM_INFO @ 165694294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly 1 test run
keymgr_kmac_rsp_err 45112455098082839674800904700383877376860978081503542999152693084026278945623 104
UVM_INFO @ 12972076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (keymgr_if.sv:403) [keymgr_if] wait timeout occurred! 1 test run
keymgr_custom_cm 43649695937169651456905615067876196935751656200258980517689459766727353239717 286
UVM_INFO @ 6449476692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_reg_block.fault_status.cmd reset value: * 1 test run
keymgr_custom_cm 5435596599002705232543313900842749951242607773934453175277880729774476716145 253
UVM_INFO @ 115347490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---