Simulation Results: lc_ctrl/volatile_unlock_disabled

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.38 %
  • code
  • 85.90 %
  • assert
  • 94.97 %
  • func
  • 96.26 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.77 %
  • toggle
  • 88.25 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.930s 1244.316us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.260s 44.616us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.560s 18.752us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.550s 22.840us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.580s 101.891us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.640s 120.288us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.560s 18.752us 5 5 100.00
lc_ctrl_csr_aliasing 1.580s 101.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.490s 323.988us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.070s 411.930us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.380s 12.508us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.690s 481.371us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 12.780s 626.174us 20 20 100.00
security_escalation 140 140 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_prog_failure 4.690s 481.371us 20 20 100.00
lc_ctrl_errors 12.780s 626.174us 20 20 100.00
lc_ctrl_security_escalation 11.840s 370.165us 20 20 100.00
lc_ctrl_jtag_state_failure 76.640s 17542.297us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.570s 1002.016us 20 20 100.00
lc_ctrl_jtag_errors 75.850s 7246.108us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 15.590s 3323.608us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.390s 994.038us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.570s 1002.016us 20 20 100.00
lc_ctrl_jtag_errors 75.850s 7246.108us 20 20 100.00
lc_ctrl_jtag_access 25.570s 6892.865us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 31.180s 1462.392us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 7.140s 5049.660us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.320s 365.412us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 32.490s 4928.534us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 18.160s 1814.872us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.730s 21.768us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.760s 754.163us 10 10 100.00
lc_ctrl_jtag_alert_test 2.240s 64.667us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 29.660s 3041.589us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.410s 12.695us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 362.680s 30321.312us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.740s 28.632us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.860s 149.960us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.860s 149.960us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.260s 44.616us 1 1 100.00
lc_ctrl_csr_rw 1.560s 18.752us 5 5 100.00
lc_ctrl_csr_aliasing 1.580s 101.891us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.410s 44.865us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.260s 44.616us 1 1 100.00
lc_ctrl_csr_rw 1.560s 18.752us 5 5 100.00
lc_ctrl_csr_aliasing 1.580s 101.891us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.410s 44.865us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
lc_ctrl_tl_intg_err 4.950s 1224.596us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.950s 1224.596us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.070s 411.930us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.100s 1685.245us 20 20 100.00
lc_ctrl_sec_cm 10.640s 959.872us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.840s 370.165us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.490s 323.988us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.390s 994.038us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.980s 3378.724us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.980s 3378.724us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 17.140s 4090.385us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.740s 5071.308us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.740s 5071.308us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 59.680s 4635.586us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 69686020171933882495494857876929838259012188593811194767397449233042246125171 2269
UVM_INFO @ 1138292208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35315001534065939027542736907640662062099888395954862083305250612774613839797 4205
UVM_INFO @ 4720606087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17889477444108719073088706856628488891424238221666211723813278423355832382760 5531
UVM_INFO @ 14210387167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12482930439993958252783086328373352059667690475687711637805614928589690603199 155
UVM_INFO @ 1040162434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58497596424522701306561311881114857787823293165415334519987647905200189405733 150
UVM_INFO @ 109342184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34235716216210462054319918201292904413056468348674738040382462572162175394584 2357
UVM_INFO @ 16471242369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 28548463519169641629850969618466617359313613594596246836488149567092849932190 3001
UVM_INFO @ 7467092749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---