Simulation Results: lc_ctrl/volatile_unlock_enabled

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.35 %
  • code
  • 86.12 %
  • assert
  • 94.83 %
  • func
  • 96.09 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 81.82 %
  • toggle
  • 88.25 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
98.83%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.970s 132.020us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.490s 17.875us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.390s 14.787us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.250s 108.252us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.820s 44.772us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.900s 39.139us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.390s 14.787us 5 5 100.00
lc_ctrl_csr_aliasing 1.820s 44.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.460s 72.466us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.490s 2605.858us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.320s 14.293us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.910s 108.408us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 21.870s 2519.682us 19 20 95.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_prog_failure 3.910s 108.408us 20 20 100.00
lc_ctrl_errors 21.870s 2519.682us 19 20 95.00
lc_ctrl_security_escalation 11.950s 439.303us 20 20 100.00
lc_ctrl_jtag_state_failure 58.070s 2378.469us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.410s 1875.931us 20 20 100.00
lc_ctrl_jtag_errors 86.830s 74310.453us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 14.440s 1415.337us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.650s 2691.340us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.410s 1875.931us 20 20 100.00
lc_ctrl_jtag_errors 86.830s 74310.453us 18 20 90.00
lc_ctrl_jtag_access 18.200s 3838.261us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.040s 6071.196us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.150s 577.087us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.690s 1490.153us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 19.210s 990.171us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.850s 1855.857us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.380s 51.813us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.240s 160.137us 10 10 100.00
lc_ctrl_jtag_alert_test 3.070s 165.946us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 23.250s 1198.755us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.450s 22.144us 10 10 100.00
stress_all 8 10 80.00
lc_ctrl_stress_all 150.740s 14594.657us 8 10 80.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.580s 20.172us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.100s 102.070us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.100s 102.070us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.490s 17.875us 1 1 100.00
lc_ctrl_csr_rw 1.390s 14.787us 5 5 100.00
lc_ctrl_csr_aliasing 1.820s 44.772us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.240s 237.491us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.490s 17.875us 1 1 100.00
lc_ctrl_csr_rw 1.390s 14.787us 5 5 100.00
lc_ctrl_csr_aliasing 1.820s 44.772us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.240s 237.491us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
lc_ctrl_tl_intg_err 4.950s 1095.700us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.950s 1095.700us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.490s 2605.858us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.660s 1458.417us 20 20 100.00
lc_ctrl_sec_cm 9.760s 124.559us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.950s 439.303us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.460s 72.466us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.650s 2691.340us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.510s 2656.072us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.510s 2656.072us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.950s 1714.291us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 13.310s 2461.753us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 13.310s 2461.753us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 65.480s 2697.955us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 5 test runs
lc_ctrl_stress_all 16569321048921245149079322411800457757042642596247494943190533909476118252321 5492
UVM_INFO @ 2638754283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 99967621243703528971009019759456666507378682130217784483471776819696469668122 517
UVM_INFO @ 235681992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 70204775091692558812704480842353127293196475935524336886882662815213552420528 10241
UVM_INFO @ 10562754244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 72316812511013203795446511416312088571657062143430513625984347458377715066858 855
UVM_INFO @ 313051479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 54855856560093688647372183943194924901132697773357866390324510376723522957113 3166
UVM_INFO @ 1186479327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 94263185251967328122228896424026897258684615000346959464084830069719554318068 247
UVM_INFO @ 1332705096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19576461651666704388147095701254698908194972698970321624664219761192127002789 150
UVM_INFO @ 712833824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81584786571603409334436585060513732769789517818417384019578675241712051812433 817
UVM_INFO @ 479041604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22558445119090167162060635295326291049837066073955863141184862356766692721315 1072
UVM_INFO @ 4022816729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 33050619113602990700926278710394053363532736668094852853812754846430747442032 2924
UVM_INFO @ 3587541534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---