Simulation Results: otbn

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.89 %
  • code
  • 87.13 %
  • assert
  • 97.54 %
  • func
  • 100.00 %
  • block
  • 99.38 %
  • line
  • 99.56 %
  • branch
  • 95.45 %
  • toggle
  • 85.91 %
  • FSM
  • 67.61 %
Validation stages
V1
99.14%
V2
99.39%
V2S
97.26%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 36.000s 51.412us 1 1 100.00
single_binary 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 39.000s 25.061us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 38.000s 14.518us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 41.000s 51.710us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 37.000s 71.581us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 41.000s 70.013us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 38.000s 14.518us 5 5 100.00
otbn_csr_aliasing 37.000s 71.581us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 106.000s 2819.582us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 86.000s 2471.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 63.000s 1688.272us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 89.000s 495.065us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 168.000s 434.730us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 188.000s 451.763us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 38.000s 20.036us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 13.000s 46.473us 5 5 100.00
sw_errs_fatal_chk 9 10 90.00
otbn_sw_errs_fatal_chk 25.000s 143.642us 9 10 90.00
alert_test 10 10 100.00
otbn_alert_test 38.000s 26.968us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 38.000s 31.869us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 19.000s 31.242us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 19.000s 31.242us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 39.000s 25.061us 1 1 100.00
otbn_csr_rw 38.000s 14.518us 5 5 100.00
otbn_csr_aliasing 37.000s 71.581us 1 1 100.00
otbn_same_csr_outstanding 31.000s 40.412us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 39.000s 25.061us 1 1 100.00
otbn_csr_rw 38.000s 14.518us 5 5 100.00
otbn_csr_aliasing 37.000s 71.581us 1 1 100.00
otbn_same_csr_outstanding 31.000s 40.412us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 39.000s 26.190us 10 10 100.00
otbn_dmem_err 40.000s 37.563us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 41.000s 85.642us 5 5 100.00
otbn_controller_ispr_rdata_err 39.000s 54.313us 5 5 100.00
otbn_mac_bignum_acc_err 37.000s 41.881us 5 5 100.00
otbn_urnd_err 12.000s 37.913us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 36.000s 28.477us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 37.000s 41.846us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 42.000s 53.231us 9 10 90.00
tl_intg_err 25 30 83.33
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
otbn_tl_intg_err 36.000s 201.191us 24 25 96.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 101.000s 252.037us 4 5 80.00
prim_fsm_check 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
prim_count_check 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 36.000s 51.412us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 40.000s 37.563us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 39.000s 26.190us 10 10 100.00
sec_cm_bus_integrity 24 25 96.00
otbn_tl_intg_err 36.000s 201.191us 24 25 96.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 38.000s 20.036us 60 60 100.00
sec_cm_controller_fsm_local_esc 36 40 90.00
otbn_imem_err 39.000s 26.190us 10 10 100.00
otbn_dmem_err 40.000s 37.563us 15 15 100.00
otbn_zero_state_err_urnd 13.000s 46.473us 5 5 100.00
otbn_illegal_mem_acc 36.000s 28.477us 5 5 100.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_controller_fsm_sparse 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 39.000s 26.190us 10 10 100.00
otbn_dmem_err 40.000s 37.563us 15 15 100.00
otbn_zero_state_err_urnd 13.000s 46.473us 5 5 100.00
otbn_illegal_mem_acc 36.000s 28.477us 5 5 100.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_scramble_ctrl_fsm_sparse 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 38.000s 20.036us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 39.000s 26.190us 10 10 100.00
otbn_dmem_err 40.000s 37.563us 15 15 100.00
otbn_zero_state_err_urnd 13.000s 46.473us 5 5 100.00
otbn_illegal_mem_acc 36.000s 28.477us 5 5 100.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_start_stop_ctrl_fsm_sparse 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 39.000s 32.020us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 37.000s 108.417us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 58.000s 393.398us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 58.000s 393.398us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 40.000s 71.545us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_stack_wr_ptr_ctr_redun 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 40.000s 542.500us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_loop_stack_ctr_redun 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 42.000s 56.457us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 42.000s 56.457us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 36.000s 29.531us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 168.000s 434.730us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 24.000s 432.662us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 229.000s 1012.405us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
otbn_sec_cm 209.000s 12198.898us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 411.000s 5998.449us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 30.000s 27.390us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 57487249217210264530164031368028668969059697020434018133855582126514060875667 405
UVM_INFO @ 2230801497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 46033975700198405269919278464012955420678251230909176167133470119512727633424 452
UVM_INFO @ 5998449103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 54127622320666777798198133255109005603286062699511953408117546037326122601172 297
UVM_INFO @ 454774196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 921740270443500556789138474992709561952215364619870006229190187240345239400 191
UVM_INFO @ 129449524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 4 test runs
otbn_sec_cm 28970591514372479625798781516232377992761713552085462709521727438918459393417 90
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 8707334 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 8707334 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 8707334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 28560152595364661305162270264920750645670235693808823580549464741014175801267 89
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 8902933 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 8902933 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 8902933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 42249133619773543806181451027140210409658276751047872615609642905004098437407 93
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 20845390 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 20845390 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 20845390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 48133029543131185391380726329841366270742156123781511395541680924933828246658 116
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 584378811 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 584378811 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 584378811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_sw_errs_fatal_chk 111383056292624348567898147717478736238331215471419155245742964598153634898614 110
UVM_INFO @ 85195257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 109452310883402494065307907819124303115199703189585822547567185787898572303266 120
UVM_INFO @ 171885585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 44708149555890138905528612758903929418721745798255354873957903243883957718278 297
UVM_INFO @ 4081157054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 66595295700309679436918660016538555754221481727834044480227360732182782587082 91
UVM_INFO @ 20055031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS) 1 test run
otbn_partial_wipe 1787126812892085409615440434074623691583228241417742717549861021193203449658 117
UVM_ERROR @ 4194482 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 4194482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_rnd.sv,233): Assertion UrndNoReseedOnReset_A has failed 1 test run
otbn_tl_intg_err 47891448156048933344634470421708284085529166698662651675649716742685901120711 144
UVM_ERROR @ 37631595 ps: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 37631595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_single 92840268203197247270161937807465464537198323741661278923498734662982157585078 108
UVM_INFO @ 179195103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---