Simulation Results: otp_ctrl

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.31 %
  • code
  • 86.10 %
  • assert
  • 95.52 %
  • func
  • 92.30 %
  • line
  • 90.43 %
  • branch
  • 86.94 %
  • cond
  • 94.05 %
  • toggle
  • 95.73 %
  • FSM
  • 63.37 %
Validation stages
V1
92.31%
V2
96.95%
V2S
96.52%
V3
25.74%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.700s 52.528us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.090s 114.375us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.070s 48.698us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.440s 332.531us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.010s 231.243us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.360s 1774.787us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.070s 48.698us 5 5 100.00
otp_ctrl_csr_aliasing 3.010s 231.243us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.390s 138.150us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.360s 141.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 17.010s 915.269us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.890s 3189.398us 300 300 100.00
partition_check 40 60 66.67
otp_ctrl_background_chks 33.430s 7499.029us 10 10 100.00
otp_ctrl_check_fail 23.850s 2022.857us 30 50 60.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 8.830s 1226.075us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 55.490s 28302.586us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 24.860s 13343.847us 10 10 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_dai_errors 25 25 100.00
otp_ctrl_dai_errs 58.520s 23015.512us 25 25 100.00
otp_macro_errors 7 10 70.00
otp_ctrl_macro_errs 61.580s 41813.863us 7 10 70.00
test_access 10 10 100.00
otp_ctrl_test_access 57.820s 11469.895us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 271.500s 52928.108us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.910s 617.658us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.760s 869.879us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 7.320s 2064.416us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 7.320s 2064.416us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.090s 114.375us 1 1 100.00
otp_ctrl_csr_rw 2.070s 48.698us 5 5 100.00
otp_ctrl_csr_aliasing 3.010s 231.243us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.040s 1722.226us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.090s 114.375us 1 1 100.00
otp_ctrl_csr_rw 2.070s 48.698us 5 5 100.00
otp_ctrl_csr_aliasing 3.010s 231.243us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.040s 1722.226us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
otp_ctrl_tl_intg_err 34.530s 19327.221us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 34.530s 19327.221us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
sec_cm_part_fsm_local_esc 207 210 98.57
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_ctrl_macro_errs 61.580s 41813.863us 7 10 70.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
sec_cm_part_fsm_global_esc 207 210 98.57
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_ctrl_macro_errs 61.580s 41813.863us 7 10 70.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.060s 5396.930us 200 200 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.890s 3189.398us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 30 50 60.00
otp_ctrl_check_fail 23.850s 2022.857us 30 50 60.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 33.590s 15363.007us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 144.340s 157398.300us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 8.830s 1226.075us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 8.630s 6352.813us 10 10 100.00
sec_cm_macro_mem_integrity 7 10 70.00
otp_ctrl_macro_errs 61.580s 41813.863us 7 10 70.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 21.210s 8729.339us 1 1 100.00
stress_all_with_rand_reset 25 100 25.00
otp_ctrl_stress_all_with_rand_reset 160.680s 63805.301us 25 100 25.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 36 test runs
otp_ctrl_macro_errs 5307513295327208455213354398852116587410095967581603814607665293216977193791 1371
UVM_INFO @ 214054305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 23588206723393417071400199952307587199300594503199415659190178325053243740176 809
UVM_INFO @ 85303055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 110432460026236551569314944236142497692586888827792082038336104050436685807583 10667
UVM_INFO @ 7140552524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 81664362009412168174383411188550089316500697115031560660322817685490207761078 2618
UVM_INFO @ 121884479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30884580006538418059485836077667813706700624879844302958067652120340695482582 211
UVM_INFO @ 66207030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 64231090664648608749759621101887386398028266400814428971520261643637275845607 11141
UVM_INFO @ 10939908952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100473388374539834265532416577896714833422150906930440995931370725072336310407 12750
UVM_INFO @ 5062458456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79232575597256062726963921838436686570312493690667052798530595427737713964075 28257
UVM_INFO @ 8797548846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 34955361774061968388001970265052323712909615440875131075037051179115251281053 8691
UVM_INFO @ 6071770591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2470879827930867142726828626084495698145953369660420616785713666065455096385 827
UVM_INFO @ 84342332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41172969084435913779920254496519587478336117616398963061102659149786817606529 845
UVM_INFO @ 86689257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104464499554370772619878737396796671282772131869529899403733237086757691025945 2968
UVM_INFO @ 279591505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 58954868290243835360144260696901040912322180207031476887482022942307539455267 10329
UVM_INFO @ 1524151858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 8301370606746047778195798823868715780482666676224567199039025712149725368180 2690
UVM_INFO @ 788001766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 82546071786105397870417194743591874088871056376265133711817592497000781341101 1475
UVM_INFO @ 540998472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35392895749130436316946578955013460120188562727195140446932307213456489236289 337
UVM_INFO @ 276818474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73126010182875147441258202250896962455395139561333489388439287752233540657052 17557
UVM_INFO @ 9945649729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26294118388956732215091710480197802032342998327241711202481214610277377108402 13308
UVM_INFO @ 773245519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 101005263674418920206728031938541803902210946362264777612318503102239583768548 6210
UVM_INFO @ 290590664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68002476133738516432093479933771052942939673371571806968237497279743034703401 3076
UVM_INFO @ 714929708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108114439239846657704724587542653901096003811224275578065028438109150745334843 8436
UVM_INFO @ 1666829295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 88812636683483685828433948629275751120223827206695884295408662596649321592518 5322
UVM_INFO @ 1127355294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93574394564170559126739522098611885310975269358715627649806644113147073458248 4652
UVM_INFO @ 8310295847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 79556513616130376899455564890533018341775565334693068315476555387643546521074 221
UVM_INFO @ 90939746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94172594867612769528971020179096629026445544652833959503913561644963105636513 15783
UVM_INFO @ 2738797813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100437754921473687593061924020573751535197139535100651576627396852793931870870 1259
UVM_INFO @ 240184237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64336400574602563104744756988075421820282189992499806128823623805886630595410 703
UVM_INFO @ 42356572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105289902185707254261415838061649340716268907952202929356272307101726810977958 12909
UVM_INFO @ 13479328417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 14821776026755814574900681908285813020856727676032526590240455104296545200142 5130
UVM_INFO @ 162005988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56775683368027948419347608040579803925834463268022405556857099586444351145559 763
UVM_INFO @ 246026654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74477480522720458942932776275156054851406305122868355127947034652973822724190 5086
UVM_INFO @ 15051017567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26589912247656957346083370956548029076194213836367745919283834152887563503384 16329
UVM_INFO @ 3697503086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67747755578037699467009761480627956645958566564728463940015719462746240002641 1415
UVM_INFO @ 132417717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6871210920988925064663428382040580325904347763384632778470063111013056888731 1435
UVM_INFO @ 1298910452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86906290217421577515294120959895487798934915916934197472168748995187725679980 1884
UVM_INFO @ 16145393488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82086790485967423623237544194228491523400872630428596776170120427577547359343 8248
UVM_INFO @ 6903159802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 22 test runs
otp_ctrl_stress_all_with_rand_reset 48169812106197772077830574588998936145989761236992969407751062931488490430052 155
UVM_INFO @ 65134726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75541940434956948332844344022379601802053926070127396137458545447762833809887 2940
UVM_INFO @ 689099269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95691332303239598218357782251651141473094229127757942061741286206959572791652 9549
UVM_INFO @ 5085620781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55339101101136483124669695286329931942726622784263633024548172904299034496925 6508
UVM_INFO @ 3528338276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81336184213889342307389140518481769910889660776950158486244244630978153517134 14127
UVM_INFO @ 43889622137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86325341174170292804136416903395030876362166145253133818687557808834926361147 109
UVM_INFO @ 454154740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59922790023546545379446340116690641308973401009844704867066127010076530920324 34728
UVM_INFO @ 3097896186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105596062873252650910850094186093917714780373236513373620557854606862028367297 6554
UVM_INFO @ 1022613481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36318159347866010836590280317719699592716918683814317155247020182202591233703 1637
UVM_INFO @ 5482180953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46518794359177205368337389865300688668303592396084787837419715872126371824321 7349
UVM_INFO @ 15332234367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84568908636877097998591169386593841245123515557064063771786609858365836876740 123
UVM_INFO @ 29741625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6626074952888879858502376913049604295645362244854166963423907577613925800865 850
UVM_INFO @ 210220484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99203600810642825901325325089357955120850823045583918496250494564031348228149 12784
UVM_INFO @ 1198392443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78198152831063224412181044781159105757943252222019794315325090228637242240572 13632
UVM_INFO @ 2670225642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69345335432641715644715905955517055530073893351565985009054824062247806045633 5439
UVM_INFO @ 1569462953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4452932225306599419250564804512389465285012854552385007875423722600697791777 1328
UVM_INFO @ 458545992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30812418329062989806697705698578184273447237738613016341431004196799880777227 19483
UVM_INFO @ 7036319313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87230598904282222562297853519951449895595289415451107530362786684292061507993 5090
UVM_INFO @ 4769773622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57623757220706356420352654992444844327465240530747717346872932446248028903479 1916
UVM_INFO @ 1055395630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36677584737698955789776610793069244418734755188844363554044806777636594679496 14309
UVM_INFO @ 3047398709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38028198610250633335144395420536115465258805637035570124885217491351991299547 343
UVM_INFO @ 14742283341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13244339929438470864256586333699094434066340033752297833117885655392068420031 4094
UVM_INFO @ 686908780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 19 test runs
otp_ctrl_stress_all_with_rand_reset 19743879680922123579730819504491480480010098998335839407906014024600131774591 26243
UVM_INFO @ 2727711751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 104296539578795753538756157099768110988270983156912293768274351620845054744384 92
UVM_INFO @ 426769107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38771001082987325744220916005341123700071092081852364796833894763985874606604 41485
UVM_INFO @ 2772841936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53874059538852045105559141746759376879384781711811071789569867304242876308384 92
UVM_INFO @ 102935466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5029893437230446765634077980190191672028372162244067540506911337217849430512 286
UVM_INFO @ 1032034148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103306628197763986302586253782824921301025732637664685106784018952900279585955 137
UVM_INFO @ 113068069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98998482146677991760724562760289694208636659461660560420405101274839223485947 4967
UVM_INFO @ 1844401694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6416633009093858889671485121950029405913084560515702337525169108230043109268 31741
UVM_INFO @ 12562587910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108212091096463490975698058250609929955588874305654172498134527338144862495218 4558
UVM_INFO @ 1032466230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52898978371122947359798832990530868564035073321513726602552911396204887239584 16544
UVM_INFO @ 16845690363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15921693890555844897722268462420316346484650616054520459855714784410582983151 2024
UVM_INFO @ 1856638439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86470001054945443567043190001783549135699902087794443116686431428749530571849 10781
UVM_INFO @ 2237471129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27565195339463113537353916216628959655128713422972642037712621478068032536774 7072
UVM_INFO @ 1154198905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6358079412545924514407758732567094190289056572261274155683140583078627206974 133
UVM_INFO @ 127399180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 194841666580563653553620495920796942487657866518670016466653841309004846892 182
UVM_INFO @ 63525138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2592442617822578336959527335876957586003282003151301900965938456761006104602 4838
UVM_INFO @ 7758550365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33771163058128802423780575670131974541445058694981906566394268503514523691431 36945
UVM_INFO @ 30769233735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77859008087833732874904680964235114099478947703696839074920357577418586194058 92
UVM_INFO @ 103461824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66610675263215966148148422097804808865299167499701100145608430186938224371932 92
UVM_INFO @ 37867276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 13 test runs
otp_ctrl_stress_all_with_rand_reset 31066849640872239672658616388159121895082660948457524354571529196848731455082 92
UVM_INFO @ 103061163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 7465885894963070106010735455832360155381654969769802564873318945121651541668 98
UVM_INFO @ 185282961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12761701097893242844582904903499836005440637373794586792087223832738127824428 92
UVM_INFO @ 26715719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12209296904284761767791736343516366165997212962145134123410124551978052258467 92
UVM_INFO @ 104397712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111659691777491267324490192387755933692107806375918971870599203165377764259162 1374
UVM_INFO @ 16012305082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73124768608164512505221088082283350402691075307767693725323273186849360895571 1195
UVM_INFO @ 6563235822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99090014959590691453062134620114164370329384675484955218130789348473556354308 92
UVM_INFO @ 60918403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48779848525380896223339439501683380631596777925890748403027899551771091247 3159
UVM_INFO @ 482951936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80435207208015651724202537326041154387939471360918420563129778561534090548099 2992
UVM_INFO @ 1396092404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6806607615583064661912985963343404154929625231581440811668380545539699222459 92
UVM_INFO @ 42207285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12540441288730080022585693389465919272414790877447340971443542521095510203241 14429
UVM_INFO @ 3560300911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61694542706231669721985974429543131670202799906706160103909035659809178209445 92
UVM_INFO @ 52870782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28322983532416802173412014817450077969876899234206994381489216382992228417457 5925
UVM_INFO @ 3104580043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
otp_ctrl_stress_all_with_rand_reset 66058261437737242843851313292572711208555998707385933044038318012468340657192 19509
UVM_INFO @ 33582123303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4387690493993147330356577202273342265479335920524442317562910275854064458642 2039
UVM_INFO @ 437171641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28572253670313017393446161190087744842712645038438734785867745894000914467540 2363
UVM_INFO @ 8809764327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 3 test runs
otp_ctrl_stress_all_with_rand_reset 97046861611536013492033475483550551973141010822896182154145124390427800282993 10282
UVM_INFO @ 28441154370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8230337459678209081403181184485270621902203598119911472572412145403887852229 2554
UVM_INFO @ 721162722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76975924662282407557685736589906543416660570883976354799572950516274859862827 5595
UVM_INFO @ 696515111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=250) 1 test run
otp_ctrl_stress_all_with_rand_reset 43643897996580271478280037450399533171544443596758108631489617452990395658611 50598
UVM_INFO @ 14851342440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 30917266812399782865390892753262417663055764368216325043882329939039218159069 386
UVM_INFO @ 10243168465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 79861223107767224174289164892876252889545825144814496697164291839684161654445 24167
UVM_INFO @ 2391790453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 80222233058935132900145872429769775755306978490655079266451554631051611325649 6542
UVM_INFO @ 1828592030 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1828643753 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1829281670 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1829488562 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1