Simulation Results: pwrmgr

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.50 %
  • code
  • 97.54 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.16%
V2S
100.00%
V3
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.970s 28.526us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.790s 48.310us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.780s 24.746us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.940s 2327.005us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.910s 36.762us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.380s 55.152us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.780s 24.746us 5 5 100.00
pwrmgr_csr_aliasing 0.910s 36.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 0.890s 138.978us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 0.890s 138.978us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.130s 194.172us 10 10 100.00
pwrmgr_lowpower_invalid 0.930s 78.518us 10 10 100.00
reset 18 20 90.00
pwrmgr_reset 2.370s 1000.000us 9 10 90.00
pwrmgr_reset_invalid 0.970s 95.752us 9 10 90.00
main_power_glitch_reset 9 10 90.00
pwrmgr_reset 2.370s 1000.000us 9 10 90.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.070s 348.075us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.090s 353.915us 10 10 100.00
disable_rom_integrity_check 7 10 70.00
pwrmgr_disable_rom_integrity_check 1.190s 1000.000us 7 10 70.00
stress_all 7 10 70.00
pwrmgr_stress_all 35.830s 10997.929us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.720s 44.126us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.300s 141.808us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.300s 141.808us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.790s 48.310us 1 1 100.00
pwrmgr_csr_rw 0.780s 24.746us 5 5 100.00
pwrmgr_csr_aliasing 0.910s 36.762us 1 1 100.00
pwrmgr_same_csr_outstanding 1.040s 219.961us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.790s 48.310us 1 1 100.00
pwrmgr_csr_rw 0.780s 24.746us 5 5 100.00
pwrmgr_csr_aliasing 0.910s 36.762us 1 1 100.00
pwrmgr_same_csr_outstanding 1.040s 219.961us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.640s 342.158us 25 25 100.00
pwrmgr_sec_cm 1.650s 659.337us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.650s 659.337us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.650s 659.337us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.640s 342.158us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.540s 852.118us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.070s 348.075us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.020s 848.163us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.940s 49.856us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.750s 45.742us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.650s 659.337us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.650s 659.337us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.650s 659.337us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.850s 44.729us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.800s 38.637us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.070s 494.369us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.780s 24.746us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.780s 24.746us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 5 10 50.00
pwrmgr_escalation_timeout 1.010s 357.082us 5 10 50.00
stress_all_with_rand_reset 10 10 100.00
pwrmgr_stress_all_with_rand_reset 11.530s 7664.183us 10 10 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 5 test runs
pwrmgr_escalation_timeout 38582048142294730567180016624904399115329158283731375829192164022345665953179 79
UVM_ERROR @ 468217070 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 468217070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 100792906821569722849573986872685354959096848958620465104284169656032605447537 79
UVM_ERROR @ 357082074 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 357082074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 99749136416237926877406285952679210398276303453411493254391570289909875661648 79
UVM_ERROR @ 387399093 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 387399093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 20512278648324288915644590444163095319560982218338960994819203133378457442082 79
UVM_ERROR @ 99015226 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99015226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 100782887661879208659175776792240169174688568490959764226233005458101467414106 79
UVM_ERROR @ 370217874 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370217874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 84705850876610264052936232020414879770268793647238210249249643639048850108413 142
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 15884797096078441695830971879251351325945962847894749202822780888793337913115 154
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 5651272666722939630354129190618889045632883286357340517276104911585332071857 108
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 20435346946603825003689492528830713577779663638784805240979530227180646372745 174
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 58317867155061122991753730263035259028317787594913454595081777104565434194353 1012
UVM_INFO @ 11545869831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 49043891244268438068826642019834058900539654732339509206869461549857312927422 631
UVM_INFO @ 10997929322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 10972993231775635610986099639086236153219184527204294039009654360848810099310 237
UVM_INFO @ 10606892040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst 1 test run
pwrmgr_reset_invalid 49507990651384267918555117018709904214518796901936273798579402860777785961967 109
UVM_INFO @ 82179885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---