Simulation Results: rom_ctrl/32kb

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.53 %
  • code
  • 98.77 %
  • assert
  • 97.53 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.150s 414.646us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.800s 179.771us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.560s 571.066us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.430s 170.927us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.580s 169.693us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.840s 127.393us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.560s 571.066us 5 5 100.00
rom_ctrl_csr_aliasing 4.580s 169.693us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.580s 548.454us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.900s 552.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.120s 641.482us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 30.510s 8632.797us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.820s 545.975us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.830s 278.114us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 9.830s 205.374us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 9.830s 205.374us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.800s 179.771us 1 1 100.00
rom_ctrl_csr_rw 5.560s 571.066us 5 5 100.00
rom_ctrl_csr_aliasing 4.580s 169.693us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.030s 273.460us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.800s 179.771us 1 1 100.00
rom_ctrl_csr_rw 5.560s 571.066us 5 5 100.00
rom_ctrl_csr_aliasing 4.580s 169.693us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.030s 273.460us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.260s 605.066us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 248.800s 1938.088us 5 5 100.00
rom_ctrl_tl_intg_err 75.860s 1138.775us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 248.800s 1938.088us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 248.800s 1938.088us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 248.800s 1938.088us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 248.800s 1938.088us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.150s 414.646us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.150s 414.646us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.150s 414.646us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 75.860s 1138.775us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
rom_ctrl_kmac_err_chk 9.820s 545.975us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.350s 13529.620us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.260s 605.066us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 248.800s 1938.088us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 744.970s 13023.655us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 89911286499143779648726931663167711180070607310891368199803397323556056507742 79
UVM_INFO @ 594685032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 99108978165064791838290323850729315336433448348718540292261883822127590170658 79
UVM_INFO @ 641482456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---