Simulation Results: rom_ctrl/64kb

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.40 %
  • code
  • 98.77 %
  • assert
  • 97.39 %
  • func
  • 99.05 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 12.060s 1059.868us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.150s 378.215us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 12.410s 286.650us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.120s 699.236us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 15.010s 1037.113us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 16.620s 1306.869us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 12.410s 286.650us 5 5 100.00
rom_ctrl_csr_aliasing 15.010s 1037.113us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.800s 726.868us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.810s 2787.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 11.400s 419.610us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 51.090s 2060.910us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 17.710s 565.815us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 10.970s 3565.999us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 15.710s 1025.419us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 15.710s 1025.419us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.150s 378.215us 1 1 100.00
rom_ctrl_csr_rw 12.410s 286.650us 5 5 100.00
rom_ctrl_csr_aliasing 15.010s 1037.113us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.170s 1413.638us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.150s 378.215us 1 1 100.00
rom_ctrl_csr_rw 12.410s 286.650us 5 5 100.00
rom_ctrl_csr_aliasing 15.010s 1037.113us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.170s 1413.638us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 46.540s 1650.740us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 615.640s 1888.599us 5 5 100.00
rom_ctrl_tl_intg_err 154.490s 2639.556us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 615.640s 1888.599us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 615.640s 1888.599us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 615.640s 1888.599us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 615.640s 1888.599us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 12.060s 1059.868us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 12.060s 1059.868us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 12.060s 1059.868us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 154.490s 2639.556us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
rom_ctrl_kmac_err_chk 17.710s 565.815us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 225.940s 6549.671us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 46.540s 1650.740us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 615.640s 1888.599us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 376.190s 42696.786us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 112306474071937077605975889916547637196624670039581174509007194144048423370472 79
UVM_INFO @ 419609899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 42485364709693981024045487747557343470189337820232843913771472253296660396844 79
UVM_INFO @ 689234931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---