| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| rstmgr_smoke | 2.110s | 297.786us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.120s | 118.414us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.190s | 68.532us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 5.740s | 1454.119us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 2.030s | 247.318us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.610s | 126.286us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rstmgr_csr_rw | 1.190s | 68.532us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.030s | 247.318us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 5 | 5 | 100.00 | |||
| rstmgr_por_stretcher | 1.350s | 206.456us | 5 | 5 | 100.00 | |
| sw_rst | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst | 3.700s | 684.375us | 5 | 5 | 100.00 | |
| sw_rst_reset_race | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.770s | 229.068us | 5 | 5 | 100.00 | |
| reset_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.870s | 2100.550us | 5 | 5 | 100.00 | |
| cpu_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.870s | 2100.550us | 5 | 5 | 100.00 | |
| alert_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.870s | 2100.550us | 5 | 5 | 100.00 | |
| reset_info_capture | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.870s | 2100.550us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| rstmgr_stress_all | 43.670s | 13615.269us | 5 | 5 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rstmgr_alert_test | 1.130s | 88.698us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 4.140s | 547.986us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 4.140s | 547.986us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.120s | 118.414us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.190s | 68.532us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.030s | 247.318us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.620s | 150.535us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.120s | 118.414us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.190s | 68.532us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.030s | 247.318us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 1.620s | 150.535us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rstmgr_sec_cm | 26.930s | 16811.916us | 5 | 5 | 100.00 | |
| rstmgr_tl_intg_err | 3.980s | 982.125us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 26.930s | 16811.916us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 26.930s | 16811.916us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rstmgr_tl_intg_err | 3.980s | 982.125us | 25 | 25 | 100.00 | |
| sec_cm_scan_intersig_mubi | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.570s | 180.319us | 5 | 5 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 25 | 25 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 10.970s | 2805.265us | 25 | 25 | 100.00 | |
| sec_cm_leaf_rst_shadow | 5 | 5 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.860s | 302.036us | 5 | 5 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 26.930s | 16811.916us | 5 | 5 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.190s | 68.532us | 5 | 5 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.190s | 68.532us | 5 | 5 | 100.00 | |