Simulation Results

Simulation Results: rstmgr_cnsty_chk

11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

70.00%

unmapped

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	10	70.00
	rstmgr_cnsty_chk_test	4.110s	11070.389us	7	10	70.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))				3 test runs
	rstmgr_cnsty_chk_test	20206479013214368440414670033304019792630050386319625879597098824827101033697	175	UVM_INFO @ 2040734009 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 2061054009 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 2081374009 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2101694009 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	113861320806472429350935438759977998485290311823118481267506777532351839301677	175	UVM_INFO @ 1896458198 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1915338198 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1934218198 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1953098198 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	78861790151086945881681403081243680944021583588334522341334184424866578264378	175	UVM_INFO @ 2024698892 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 2044858892 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 2065018892 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2085178892 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16