| V1 |
|
100.00% |
| V2 |
|
85.83% |
| V2S |
|
100.00% |
| V3 |
|
45.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.510s | 968.200us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.720s | 16.781us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.870s | 25.520us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.230s | 171.464us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.080s | 69.911us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.230s | 22.301us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.870s | 25.520us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.080s | 69.911us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 3.890s | 3369.727us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 6.340s | 4073.313us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 261.840s | 392757.057us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 261.840s | 392757.057us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 5.690s | 11999.993us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.860s | 17.571us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.950s | 55.193us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.590s | 408.817us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.590s | 408.817us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.720s | 16.781us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.870s | 25.520us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.080s | 69.911us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.040s | 27.589us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.720s | 16.781us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.870s | 25.520us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.080s | 69.911us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.040s | 27.589us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.290s | 109.949us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.690s | 381.335us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.690s | 381.335us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 10 | 10.00 | |||
| rv_timer_min | 12.160s | 656.477us | 1 | 10 | 10.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.810s | 155.779us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 17 | 20 | 85.00 | |||
| rv_timer_stress_all_with_rand_reset | 57.900s | 37904.334us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 27 test runs | |||
| rv_timer_min | 90024073362777083886540088294834280241982759416859302899902369856992980250473 | 75 |
UVM_INFO @ 60439365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 86955003990956722865726910806523684951821950913153809701079479841397879546573 | 76 |
UVM_INFO @ 193100950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 13047378436606055069470403365917322811083835876183519277973941681854358901272 | 75 |
UVM_INFO @ 91599882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 56341128375720349791560930258638846841721490733693856101199831330508464685890 | 76 |
UVM_INFO @ 522153786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 29821442038099418219056921687029810971358853148284514305576839002954196091849 | 75 |
UVM_INFO @ 79007340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 91544549884751966995742510964505835560616544765181899222453255675978808849775 | 75 |
UVM_INFO @ 1528308742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 36437001872598803789072240930674188423133153957846991794356462524411427769933 | 76 |
UVM_INFO @ 88557549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 11360761621261842639002928695757915651252869951682807298656637840933668000291 | 75 |
UVM_INFO @ 167123072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 40222003163559224619018219969084340651984886564412836496598995090824843978369 | 75 |
UVM_INFO @ 656476912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 112228361880452428072876614228411795888895297457061777548733744481844302545472 | 77 |
UVM_INFO @ 205427193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 29165299402481029895255080353742131823676084093028710450190405527250815259230 | 75 |
UVM_INFO @ 120477251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 110834606674128855242121266474218192179715164291314626452390126784088318660477 | 75 |
UVM_INFO @ 88563711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 42944121677424400200554267567369889447814000569822790165734581610693271971163 | 75 |
UVM_INFO @ 808049559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 42872480452455639992181349742201599058497695324328303023621611547339609055041 | 75 |
UVM_INFO @ 979226027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44145628412478014582650781094679263843777922843043391651628079396450479909333 | 76 |
UVM_INFO @ 401098653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 46741637130045997620690989644671127998890613170847098590592159822736659097456 | 77 |
UVM_INFO @ 129801658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 93758383890627687688485342347551215787154212825031508563511030409247773327918 | 75 |
UVM_INFO @ 111282118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 14432492758052457624516180684866143645501863532952317256503639292072711587841 | 75 |
UVM_INFO @ 344689709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35438547487314024933174644724552463577692925149182709362950078165941818942882 | 75 |
UVM_INFO @ 1132296689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 110610632184031894757779641974349230654795398194202548430019175946630446619551 | 75 |
UVM_INFO @ 216951662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 70819072025567078010184880102511297187800763406022627115038188666798207108722 | 75 |
UVM_INFO @ 615016301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 63629333377211792562720221119140156418614538560543942874045008760743677356410 | 75 |
UVM_INFO @ 765316907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 29659446935344751307601741296898886325941258379122182167066615781992936320565 | 75 |
UVM_INFO @ 2718129102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44406165806057132618986088082607028070793500576314743539237059751013131381384 | 75 |
UVM_INFO @ 347895478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 81067916454062254562302188196112497142902305842135415185668583171971964358762 | 76 |
UVM_INFO @ 3369726987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114283772713309324436433662895140811362890862961364560784657359157214863846182 | 75 |
UVM_INFO @ 462649187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 110118172104873914674929165552820989935561641202017203384979934038283514319523 | 75 |
UVM_INFO @ 377355756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 10 test runs | |||
| rv_timer_max | 21707666574015357229048748435004830645384938317194972243405320261623193958384 | 75 |
UVM_INFO @ 155778760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 105583253124103921379311744279660246034422388151308046444961357860170158506909 | 75 |
UVM_INFO @ 250846920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 114421756657052816059891117431502259935733927758971787224502785933801900629416 | 75 |
UVM_INFO @ 106537531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 36893568350250116910848729871676139209355812447190739450296060329814173484040 | 76 |
UVM_INFO @ 471992199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 1023239012866860835610021674487442552666511080186928549359393976114478785293 | 75 |
UVM_INFO @ 87847736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 101913535690115021391704863611327632096494918075270678069101906701851703030075 | 75 |
UVM_INFO @ 878521561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 5335766836532742577982176956851690707749765478150457690596243298242456667954 | 75 |
UVM_INFO @ 342083915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 84382140720041988256930609080913646006442438496586187910052420615243485269403 | 75 |
UVM_INFO @ 85409496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 37097192615444962390786713421298293205413635385327291342358171108221244158356 | 75 |
UVM_INFO @ 51116337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 8532165241817440560402967523143013621472739361162723122607090819948856827190 | 75 |
UVM_INFO @ 48953389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 10743137311751880243852178387739404067519983450330559637205470216330712052559 | 256 |
UVM_INFO @ 11312228109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 105141289025462489158093284847957753354432804327675476766013189911053522864453 | 186 |
UVM_INFO @ 3335780068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 1 test run | |||
| rv_timer_stress_all_with_rand_reset | 72119386428733315851487173795350782844374561819625453389147222227797994432784 | 436 |
UVM_INFO @ 4553734188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|