Simulation Results: spi_host

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.07 %
  • code
  • 95.03 %
  • assert
  • 96.41 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 36.000s 1350.742us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 27.740us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 19.170us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 576.576us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 3.000s 30.204us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 40.396us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 19.170us 5 5 100.00
spi_host_csr_aliasing 3.000s 30.204us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 20.476us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 92.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 58.093us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 12.000s 1044.869us 10 10 100.00
spi_host_error_cmd 2.000s 29.135us 10 10 100.00
spi_host_event 28.000s 4687.399us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 4.000s 289.268us 10 10 100.00
speed 10 10 100.00
spi_host_speed 4.000s 289.268us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 4.000s 289.268us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 294.000s 36500.281us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 9.000s 342.398us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 73.036us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 4.000s 289.268us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 4.000s 289.268us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 36.000s 1350.742us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 36.000s 1350.742us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 197.000s 28931.890us 10 10 100.00
spien 10 10 100.00
spi_host_spien 199.000s 29596.074us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 585.000s 266255.597us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 6.000s 425.680us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 12.000s 1044.869us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 4.000s 27.071us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 22.725us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 316.787us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 316.787us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 27.740us 1 1 100.00
spi_host_csr_rw 2.000s 19.170us 5 5 100.00
spi_host_csr_aliasing 3.000s 30.204us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 22.141us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 27.740us 1 1 100.00
spi_host_csr_rw 2.000s 19.170us 5 5 100.00
spi_host_csr_aliasing 3.000s 30.204us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 22.141us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 404.874us 25 25 100.00
spi_host_sec_cm 2.000s 1097.764us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 404.874us 25 25 100.00