Simulation Results: sram_ctrl/ret

 
11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 145.338us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 50.954us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 45.292us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 200.522us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.608us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 59.345us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 45.292us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 22.608us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 12.000s 724.420us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 8.000s 1491.962us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 13.000s 456.245us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 222.000s 3988.031us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 9.000s 576.322us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 19.000s 1794.547us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 9.000s 1028.485us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 12.000s 567.631us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 72.543us 8 8 100.00
sram_ctrl_partial_access_b2b 354.000s 119989.907us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 25.403us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 361.628us 0 8 0.00
sram_ctrl_throughput_w_readback 3.000s 403.516us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 2807.179us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 140.375us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 62.000s 20779.870us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 20.145us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 160.710us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 160.710us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 50.954us 1 1 100.00
sram_ctrl_csr_rw 2.000s 45.292us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 22.608us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.989us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 50.954us 1 1 100.00
sram_ctrl_csr_rw 2.000s 45.292us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 22.608us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.989us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 509.781us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 1621.466us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 510.400us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 1621.466us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 510.400us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 2807.179us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 2807.179us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 45.292us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 12.000s 567.631us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 12.000s 567.631us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 12.000s 567.631us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 9.000s 1028.485us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 35.281us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 509.781us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 35.951us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 145.338us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 145.338us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 12.000s 567.631us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 1621.466us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 9.000s 1028.485us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 1621.466us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 1621.466us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 145.338us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 1621.466us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 33.000s 2898.186us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 7179280588217323031135725456553402159250866739393821942837198969982910397348 86
UVM_INFO @ 25403278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 82294818818495891330410139754178370052182391097702266378742448438807925534112 86
UVM_INFO @ 50093823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 91674118226061521673348174071746221170379932139547938351230362208839033599682 86
UVM_INFO @ 29909935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 113019433005599323424432571376298074492599675089452213344982817544176130044018 86
UVM_INFO @ 361627674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 106032227401760257354757565166623321419481286670978865619858123348293816582007 86
UVM_INFO @ 25975113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 78815476920825251909949035029049548585158932520297641043363775507582875252122 86
UVM_INFO @ 160470802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 23602797901625264296991840655577041417358712514438377735457447532326941149281 86
UVM_INFO @ 70945650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 13516539333826247195696724319350137300118452680608570688756300364703290874524 86
UVM_INFO @ 57714960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 9408227420644254518091578734789710006333609629869401437227100387493515873034 86
UVM_INFO @ 26786683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 65999089235817971395678761266156664093802505556592835513835486277180458000741 86
UVM_INFO @ 45948581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 480014227727461853265192222355759224903724698150061864004038655604351609967 86
UVM_INFO @ 219210970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 83993833100985196327868951141070325499246893068862777012778664536129252018552 86
UVM_INFO @ 27853571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 44612980484417792489277533537385212013693801827733835052606198247575044983519 86
UVM_INFO @ 111904594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 61123196441453120615369109131916541640769213754198758249256978077444899795315 86
UVM_INFO @ 34877959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 94054504850285217864456580090174069757504734318870495250112007980832806095204 86
UVM_INFO @ 111295188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 25366888755829563852806688186634580034269476288297544100360244739691124079239 86
UVM_INFO @ 28795091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 98462712316413265815645448225998756777405585184308605149905431550172632292985 86
UVM_INFO @ 173336910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 80323765844468944737319643073178061022532307922472422387573985464507125887654 86
UVM_INFO @ 39026901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 101505662231593270320152810365271818761100618392575296926732930693445319907111 86
UVM_INFO @ 403516435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 52109334988659984274477561138362581242113157026979869048436422248915024350388 86
UVM_INFO @ 23747479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 19182475751137714728748161753713787517929961549268420602003930109034299396467 86
UVM_INFO @ 261447547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 39581697186089890270068458874161140601319092780287367038676855053963076161036 86
UVM_INFO @ 118196281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 112162891094464941091726715347509315626549779558842689837506268464423796066971 86
UVM_INFO @ 60121787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 69161802580446240371100594040614186106484517361985570713639471435077438685481 86
UVM_INFO @ 25191689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---