Simulation Results

Simulation Results: uart

11/07/2026 02:34:57 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.71 %

code
92.64 %

assert
97.98 %

func
99.53 %

line
99.48 %

branch
98.14 %

cond
98.25 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		97.23%
V2S		100.00%
V3		90.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	14.170s	5906.515us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.910s	66.354us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	0.990s	14.457us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.010s	281.144us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.040s	36.672us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	1.290s	149.337us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	0.990s	14.457us	5	5	100.00
	uart_csr_aliasing	1.040s	36.672us	1	1	100.00

386/397 passed

97.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	128.060s	69114.425us	10	10	100.00
parity				20	20	100.00
	uart_smoke	14.170s	5906.515us	10	10	100.00
	uart_tx_rx	128.060s	69114.425us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	343.270s	294948.712us	10	10	100.00
	uart_rx_parity_err	94.080s	164135.573us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	128.060s	69114.425us	10	10	100.00
	uart_intr	343.270s	294948.712us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	378.390s	227196.418us	10	10	100.00
fifo_overflow				10	10	100.00
	uart_fifo_overflow	70.300s	76120.140us	10	10	100.00
fifo_reset				200	200	100.00
	uart_fifo_reset	289.910s	184343.005us	200	200	100.00
rx_frame_err				10	10	100.00
	uart_intr	343.270s	294948.712us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	343.270s	294948.712us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	343.270s	294948.712us	10	10	100.00
perf				9	10	90.00
	uart_perf	787.390s	25939.076us	9	10	90.00
sys_loopback				10	10	100.00
	uart_loopback	8.580s	10893.332us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	8.580s	10893.332us	10	10	100.00
rx_noise_filter				2	10	20.00
	uart_noise_filter	28.430s	47355.371us	2	10	20.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	10.970s	35179.871us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	23.980s	6705.370us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	41.180s	7505.534us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	1093.060s	152194.045us	10	10	100.00
stress_all				8	10	80.00
	uart_stress_all	615.530s	141770.404us	8	10	80.00
alert_test				10	10	100.00
	uart_alert_test	0.930s	82.091us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	0.990s	16.516us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	2.590s	719.635us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	2.590s	719.635us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	0.910s	66.354us	1	1	100.00
	uart_csr_rw	0.990s	14.457us	5	5	100.00
	uart_csr_aliasing	1.040s	36.672us	1	1	100.00
	uart_same_csr_outstanding	1.120s	108.762us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	0.910s	66.354us	1	1	100.00
	uart_csr_rw	0.990s	14.457us	5	5	100.00
	uart_csr_aliasing	1.040s	36.672us	1	1	100.00
	uart_same_csr_outstanding	1.120s	108.762us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	1.240s	68.132us	5	5	100.00
	uart_tl_intg_err	1.740s	201.627us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	1.740s	201.627us	25	25	100.00

18/20 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				18	20	90.00
	uart_stress_all_with_rand_reset	78.900s	6313.941us	18	20	90.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				7 test runs
	uart_noise_filter	43336515048221630219270850049273742962056029261385571562150150669495658526224	77	UVM_ERROR @ 41424438973 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 42473655069 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 42629388517 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0 UVM_ERROR @ 42629531373 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
	uart_noise_filter	57336676914020693445679205451203535264595897545259206313267639134002404821351	77	UVM_ERROR @ 13005648982 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 13274084611 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 13274135893 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 13274161534 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (122 [0x7a] vs 247 [0xf7]) reg name: uart_reg_block.rdata
	uart_noise_filter	51072417719498363820369154375356766077392144160527101941799533384933718341047	74	UVM_ERROR @ 9535185 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 10743528 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 11785203 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 13785219 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	101301740451803910530378539422812067007046109964359985729438343158395563413374	75	UVM_ERROR @ 286523777 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 299759177 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 299876825 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 304269017 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	71387856490299974356665692115396969395767300480895999173710719366644666625374	74	UVM_ERROR @ 4024084439 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 5759834439 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 5759834439 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 9699834439 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_stress_all	114054635699066119668765294759346021959513591142909687715007857014202384391511	90	UVM_ERROR @ 29023862412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 29030822412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 29031382412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 29031902412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	7987105106327603745133191709257488787532207844466882926986271278539014062697	89	UVM_ERROR @ 1814695426 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_INFO @ 2081905897 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/856 UVM_ERROR @ 2213823619 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0 UVM_ERROR @ 2213906953 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				2 test runs
	uart_noise_filter	77250861275075201748608881941087717328081952618344748174547488100404491517925	75	UVM_ERROR @ 6213480470 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 6213909041 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (107 [0x6b] vs 254 [0xfe]) reg name: uart_reg_block.rdata UVM_ERROR @ 6771765626 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 6771765626 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	92582935176625011413852585878860887533491245310754514196637836829146825045483	184	UVM_ERROR @ 13206518589 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 13206629700 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata UVM_ERROR @ 13207333403 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 13207407477 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				2 test runs
	uart_stress_all	107323084111967210348096894061828001544822322088054894496907091353983449053885	75	UVM_ERROR @ 452400562 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 464000562 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 472400562 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 499400562 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_noise_filter	92163321087468536575031177730655825887123810566430715395895274756762802437222	82	UVM_ERROR @ 244307229071 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 244307229071 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 244410657539 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 245035085486 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 10, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty				1 test run
	uart_perf	58467969346435668598800351649288658755584319821920259495470240017305654928156	74	UVM_INFO @ 578253153 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9 UVM_INFO @ 757311200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9 UVM_INFO @ 4160138609 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9 UVM_INFO @ 8457504129 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [] vs [*]) Interrupt: RxWatermark				1 test run
	uart_noise_filter	6376036307245724515287233369293578014057017983550792304954238316534756705863	74	UVM_ERROR @ 88019386 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark UVM_ERROR @ 89959386 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark UVM_ERROR @ 89959386 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark UVM_ERROR @ 93559386 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark