Simulation Results

Simulation Results: adc_ctrl

18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.50 %

code
96.14 %

assert
92.71 %

func
13.66 %

line
98.86 %

branch
97.40 %

cond
87.39 %

toggle
99.76 %

FSM
97.30 %

Validation stages

V1		100.00%
V2		49.15%
V2S		100.00%
V3		20.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	15.520s	5850.603us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	2.510s	862.066us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	1.870s	340.905us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	5.880s	2481.525us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.130s	2987.702us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.730s	586.477us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	1.870s	340.905us	5	5	100.00
	adc_ctrl_csr_aliasing	3.130s	2987.702us	1	1	100.00

87/177 passed

49.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.090s	520.261us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.270s	482.648us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	1.900s	388.592us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.090s	487.364us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	1.610s	304.077us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.090s	501.953us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	1.760s	293.693us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.150s	495.484us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	9.540s	3437.404us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	97.290s	42432.892us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	209.840s	115961.476us	10	10	100.00
stress_all				0	10	0.00
	adc_ctrl_stress_all	32.330s	143131.895us	0	10	0.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.240s	514.047us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.200s	532.254us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	3.880s	404.697us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	3.880s	404.697us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.510s	862.066us	1	1	100.00
	adc_ctrl_csr_rw	1.870s	340.905us	5	5	100.00
	adc_ctrl_csr_aliasing	3.130s	2987.702us	1	1	100.00
	adc_ctrl_same_csr_outstanding	8.260s	4526.991us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.510s	862.066us	1	1	100.00
	adc_ctrl_csr_rw	1.870s	340.905us	5	5	100.00
	adc_ctrl_csr_aliasing	3.130s	2987.702us	1	1	100.00
	adc_ctrl_same_csr_outstanding	8.260s	4526.991us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	11.230s	4278.031us	5	5	100.00
	adc_ctrl_tl_intg_err	21.890s	8007.879us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	21.890s	8007.879us	25	25	100.00

2/10 passed

20.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	10	20.00
	adc_ctrl_stress_all_with_rand_reset	7.500s	1735.517us	2	10	20.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				98 test runs
	adc_ctrl_filters_polled	4946229809242936631834953818498692990444709666747203770659570450649521437752	386	UVM_INFO @ 520260918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	100183550157482264525925681145125897029798337777751573036718212234500526346889	386	UVM_INFO @ 407767288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	106860305272941301523610307745355819025854572529133656322783675523559957430084	386	UVM_INFO @ 354109426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	97072305515360750545611165679086287842774639152622935794184336622654501664748	386	UVM_INFO @ 435494831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	52880883839923222023937812174429798881226535111960438734080358847618444641290	386	UVM_INFO @ 377320159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	110541804611377955598212412761836264601000790942324893464060279954632944819591	386	UVM_INFO @ 381306604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	44314854165331741713668866655642910809062338944585762952410470322553303907683	386	UVM_INFO @ 441390463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	95028249280227267647057003005119319432129472063932148282659606754747457583150	386	UVM_INFO @ 370075909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	114764123272216383214005610520812814820186995676038914068353935958915247741749	409	UVM_INFO @ 1118782510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	57425930491509658866502476548650599118932336161815529256236284064552678974856	411	UVM_INFO @ 11989618332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	29127083258297423784565135594614400698585586725848301999076450303377143206184	386	UVM_INFO @ 312293477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	1663818775919223940664751107399818737564337857235829901288696868009235508613	386	UVM_INFO @ 499356961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	55857406229530543534675433327734425154349871293083545517161275660290443184471	386	UVM_INFO @ 417311650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	36107448150765127754568528117506143897748917187290557759874184372279846842715	386	UVM_INFO @ 393888021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	53617550591279732871481352918065546747902452330282578955582444769143147599576	386	UVM_INFO @ 524563840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	7243174158226443581559887834698101789175012644905888190670858984789111859121	386	UVM_INFO @ 501953389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	103265420555610514094226410159739395323931898139143477095502415193787750719591	386	UVM_INFO @ 483120050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	5974771316823109083881554961750411472058152659388530808123125928384163735532	386	UVM_INFO @ 293693104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	33761808234113955042097316906807973046368886813744665001764980980083914079873	406	UVM_INFO @ 4095825576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	51556897935078351980155097319803128858553358860728013853391238128790492073019	387	UVM_INFO @ 697533970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	74409615517919059749648589772622037981394937670332541101139371568411324039693	386	UVM_INFO @ 313974276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	37542910410843719909285484491734733154953325041030807472385192801101710239057	386	UVM_INFO @ 494018746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	27213434704593817703014510952065686207805622510751384920755061860795869590565	386	UVM_INFO @ 290573075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	62632062918745937851697278165705290515508174533285881747656141995501016017054	386	UVM_INFO @ 518243249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	82796244279510591769863764757456038051615307393325711319173230735104041066105	386	UVM_INFO @ 433770214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	54623185435784179672337551184142041727458530410302883416120265081160200098835	386	UVM_INFO @ 504506743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	59884391836998707850218150709874678936120337077267355910784589411869906215936	386	UVM_INFO @ 356361327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	1675794218614280597821271324799073177289813695449440616927919526465451186807	386	UVM_INFO @ 376862390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	54816155847477019181456361271379042613073501795647019024746166869950535268135	501	UVM_INFO @ 143131895077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	56100818194286644006560739812308368531054246676400578209535219359434943044289	386	UVM_INFO @ 428435971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	53995907866953747450795566955961944422321813249910084489336618286416404345861	386	UVM_INFO @ 355535696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	98099996514656832897417626612385566960950815699020240399265002773980130047673	386	UVM_INFO @ 438144334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	32502927673783587258496014380737690169308599678310562016209266151758885624424	386	UVM_INFO @ 373831174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	52503700544533555634175455905345300751645268342557389717055407692638967824976	386	UVM_INFO @ 364201152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	23312710052922031580123341348362275044629049965462056336438289095183292608588	386	UVM_INFO @ 412494788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	78689334473805486164327034281603774989101815189324957551251632570058830267714	386	UVM_INFO @ 448803089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	97556731942814835417031949148106640088336239070200793060457712698817062447	386	UVM_INFO @ 508615565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	17474827640755915225116739210575976810540185176587290289095997215454206411508	392	UVM_INFO @ 700613878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	47813559103736405070746009098721447014959812438416570370217380906222475056462	389	UVM_INFO @ 6391168250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	85718529999839768851876034433164550448544957799182000659991141665137417441873	386	UVM_INFO @ 467231148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	3469508167578178494931615005112516157728742694150796568518164037546636848000	386	UVM_INFO @ 316054289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	18955395518093985913513302749295131064932012711921750617534259939234602981695	386	UVM_INFO @ 413661887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	90190289382401487529990166155338796651835146649058082176919946186233607817229	386	UVM_INFO @ 416529193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	57604043063129913580803867047528128493519794529279130116485627938011672141413	386	UVM_INFO @ 445390642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	98004026752852176719269542785487311412397585249078788933088751803167670479716	386	UVM_INFO @ 515629439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	105363316148362647229754484297558247297028371772661667165773253967497086189184	386	UVM_INFO @ 485059371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	71638101961538290191357846330104985374792120044810117849763071134756339427320	386	UVM_INFO @ 321077831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	8633990216113721160280462197467484599174962660913430818367139798382584642982	387	UVM_INFO @ 811475733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	97970763917853796023869151786250700075351499809439300347535020913834597321235	386	UVM_INFO @ 287110297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	56411224808759271219232775270375273409728047699832388340829584060902649064907	386	UVM_INFO @ 408728457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	44195447165482222299959033628504343303066716062554793334966201517043346808063	386	UVM_INFO @ 383582253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	107390607550501282352482290712112674150685622802297265943958769305220931679554	386	UVM_INFO @ 386099089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	32516272885719096796277269663862491635111324526386264472652195660361340340419	386	UVM_INFO @ 399286597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	77454049712537099537816011294506872231682488794634781750531704399807396593115	386	UVM_INFO @ 410764606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	88729893845703709688611541696643445655138567249268462240989802172222490792136	386	UVM_INFO @ 310585128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	53845487273706619806338265914061306638847807918807545336712607416932080937303	386	UVM_INFO @ 373428107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	85034588796047038453312722710835224821967880898657398422182409157869510630119	435	UVM_INFO @ 1646217588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	5389503180217248296201798806824296387645280175189507120704272896511327226753	401	UVM_INFO @ 11489025850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	92266919032202839002157273936557381137856446695823309444118284551528047048503	386	UVM_INFO @ 367612581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	86223739050292265876170961965516029911545132089283116286620881379116351074209	386	UVM_INFO @ 482648203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	26326964748084495747603140106459326836031911464962746425130013391897333844726	386	UVM_INFO @ 388592348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	11345274015000494455988695145446915048009552674769715848272887467679301581312	386	UVM_INFO @ 487364290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	8807010980412703464840591302378799959341049095780270796203029199144203043944	386	UVM_INFO @ 334509957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	107622401073960169327316468363555325711556819029930137938546270102379103761460	386	UVM_INFO @ 348760208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	90823163534289139810326093590719007582226057830444746528828237498305315860483	386	UVM_INFO @ 320412314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	72348800779698615675373823536038474066366011707299022630168132254584247006564	386	UVM_INFO @ 375808880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	26247299184264911986286686379859895645809391851333607809046036526334405814947	392	UVM_INFO @ 976141135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	83525711912944699878594491746490813206527156793087755861418370859622694587043	387	UVM_INFO @ 769107986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	27857376191818103824787578426224799457050533477994585136040800102466883264762	386	UVM_INFO @ 471979368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	106526547257341666075210926996523637927994214405229384676107809313969095807630	386	UVM_INFO @ 433215187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	3343480443332665851168758972305362825994432545440152115670999548271004303945	386	UVM_INFO @ 482625100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	102058983337257615815956901102990986249362369857313099801871239306529282250309	386	UVM_INFO @ 395883589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	66884273177061330218446077892083079070289072097509391660456301036828181090373	386	UVM_INFO @ 393778144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	104493661130916292756280377028019863142817404488062366575887540692758420787106	386	UVM_INFO @ 445112481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	92105418841451554833540708868932993439069270733233001069940935346965862709194	386	UVM_INFO @ 460745075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	30054556302526288342171495374090829234235105060545707671550504318907976773004	386	UVM_INFO @ 407698768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	98762342397480237680402773889249456341624280630338031830252858087360665893455	414	UVM_INFO @ 2887441803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	59989795667665950750113812595124819089035499788586133842576972295412556593468	387	UVM_INFO @ 614736659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	92693545847292551052519890034562631059694323975934496750609519829057488765953	386	UVM_INFO @ 514013222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	71884576975605537243986368239741900951753693402975587372915845966889870424930	386	UVM_INFO @ 298767883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	107045359063457620441380904329270987029088972868836254421605707799808287556457	386	UVM_INFO @ 387962975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	96973987201847830047026197541772346369521166813741913566968471406910056462088	386	UVM_INFO @ 325858558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	108623446159924423204887797998317595697461764373626675858898199368042181233988	386	UVM_INFO @ 304077247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	33769315320577450385173720731348921618229335340832078093633784793931028101755	386	UVM_INFO @ 555660501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	18401013881993603581335983478470522427450207363670239611251787645899372321094	386	UVM_INFO @ 495484453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	82448218824265517663915720524876338397555609659818586414752514715032912956902	386	UVM_INFO @ 271158667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	50845222415569640662782959276164428827577411513662753891906611816455283691535	413	UVM_INFO @ 902919695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	100912570263840582307186933363304474904082904458085820977777382774725153035246	389	UVM_INFO @ 6663052187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	93519964668947544245798637667992965583730047925043989252279074621286104919546	386	UVM_INFO @ 284844216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	58591157382055877139272631371027944236566308725852672330817721078488741395311	386	UVM_INFO @ 444197184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	12044122000067067373152413039152210434863998611273025924870804419026852558445	386	UVM_INFO @ 441055310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	42187797351768340012457438370818997851950441128227755795933484319317072349960	386	UVM_INFO @ 471950688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	99794662835283863852536730454025044581657496182115632941441399405865331331766	386	UVM_INFO @ 450938904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	83931141755067177622879122379522783063984413980866039071473082645721587161927	386	UVM_INFO @ 332564574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	4133838190422883481252843995124480221777374471259043991450592920760387822855	386	UVM_INFO @ 492123264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	59341943588474960046023899079312168811781852613340812345258134474926672683456	386	UVM_INFO @ 296798072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	115556411498799649519445211536426218010762432733620233578690627025183840204390	392	UVM_INFO @ 644671268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	41164049012704396938790058168538542545313754681838475579558975083965604097616	387	UVM_INFO @ 820668834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---