| V1 |
|
100.00% |
| V2 |
|
88.36% |
| V2S |
|
98.54% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.840s | 1217.592us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.390s | 69.801us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 10.610s | 433.356us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 278.890s | 5209.674us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 50.900s | 2269.346us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 8.370s | 68.131us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 10.610s | 433.356us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 50.900s | 2269.346us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 315.270s | 12904.054us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 79.290s | 5610.433us | 50 | 50 | 100.00 | |
| entropy | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 2584.540s | 64868.883us | 24 | 25 | 96.00 | |
| sig_int_fail | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 81.850s | 16307.949us | 49 | 50 | 98.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.840s | 1217.592us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 67.270s | 5658.949us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 76.540s | 3081.495us | 50 | 50 | 100.00 | |
| ping_timeout | 16 | 50 | 32.00 | |||
| alert_handler_ping_timeout | 464.820s | 226017.447us | 16 | 50 | 32.00 | |
| lpg | 99 | 100 | 99.00 | |||
| alert_handler_lpg | 3320.840s | 720354.213us | 49 | 50 | 98.00 | |
| alert_handler_lpg_stub_clk | 2953.560s | 135804.308us | 50 | 50 | 100.00 | |
| stress_all | 48 | 50 | 96.00 | |||
| alert_handler_stress_all | 3164.990s | 70890.418us | 48 | 50 | 96.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 25.990s | 1131.161us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.340s | 121.388us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.110s | 20.793us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 24.740s | 798.788us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 24.740s | 798.788us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.390s | 69.801us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 10.610s | 433.356us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 50.900s | 2269.346us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 46.310s | 1224.069us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.390s | 69.801us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 10.610s | 433.356us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 50.900s | 2269.346us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 46.310s | 1224.069us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 384.720s | 5495.313us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 384.720s | 5495.313us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 384.720s | 5495.313us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 384.720s | 5495.313us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1138.410s | 64611.066us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 80.140s | 2328.617us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 80.140s | 2328.617us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 384.720s | 5495.313us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.840s | 1217.592us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.840s | 1217.592us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.840s | 1217.592us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.840s | 1217.592us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 81.850s | 16307.949us | 49 | 50 | 98.00 | |
| sec_cm_lpg_intersig_mubi | 49 | 50 | 98.00 | |||
| alert_handler_lpg | 3320.840s | 720354.213us | 49 | 50 | 98.00 | |
| sec_cm_esc_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 81.850s | 16307.949us | 49 | 50 | 98.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 2584.540s | 64868.883us | 24 | 25 | 96.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 2584.540s | 64868.883us | 24 | 25 | 96.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 52.250s | 1248.392us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 10 | 50.00 | |||
| alert_handler_stress_all_with_rand_reset | 312.850s | 4903.285us | 5 | 10 | 50.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 31 test runs | |||
| alert_handler_ping_timeout | 100713565557405927803409014700264347659186333300301371637098223065343312010380 | 87 |
UVM_INFO @ 4540105597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 85247080299397876614779516194909361414963608149379283765164578244400080358634 | 90 |
UVM_INFO @ 1620603761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy | 104348694506989873784070849376929537260057613182505882319384726086334591126612 | 80 |
UVM_INFO @ 15417891432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 60640938467072408073004745947736135645250814653531883802307475382526990150137 | 123 |
UVM_INFO @ 6997182627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 115748399382554383937518153203922735027610624910982413833838567934671602501354 | 114 |
UVM_INFO @ 4716514648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80684272471336394591599677108696246350824244231436198125336508999049406819960 | 145 |
UVM_INFO @ 36938418504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 113899018824611799246119254599652614445716641157372346699384826526426461543575 | 111 |
UVM_INFO @ 35591818886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 12876041594861192009059949463798480551878862370887184198993493025130122648247 | 117 |
UVM_INFO @ 6188189127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 84097007088373483540593711878294367905867609248044325014633564543541307482799 | 126 |
UVM_INFO @ 6089844306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 67536103514510835973596283167941249696063167686302515584383306511381003738144 | 154 |
UVM_INFO @ 226017447080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 87703568910806732787164061134601073306758932668879126914745091205657545525833 | 84 |
UVM_INFO @ 3605274567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 19276832819766174793289530036500962438693545616470408634362615173835280957170 | 96 |
UVM_INFO @ 3409019291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16088998769161236081640186860664411543564518572012194115625878576450821475120 | 93 |
UVM_INFO @ 15982248311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 81727752259095246979289186331010807281290849967199294107849202429645219877204 | 117 |
UVM_INFO @ 4988788396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 23525873263352601464736363989648755534774916304588037146519686253366367156134 | 106 |
UVM_INFO @ 5482037359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 48825541876458214674487421541165976925361027902040140326469092072143254900883 | 114 |
UVM_INFO @ 25662534554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 44493901406840985885770174104524666454046908923085945164881280792425676881866 | 92 |
UVM_INFO @ 6590288121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 115694025566874861516489119639969605857983277736788456518153650403630604250046 | 124 |
UVM_INFO @ 5644827117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 24025508121128414557202418798242502746258146838530464378611165127192559982345 | 84 |
UVM_INFO @ 2471732087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 79104811047182849826015512936036601706818537291914378375469468103416709996977 | 87 |
UVM_INFO @ 1786888963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 20512275140500519117348200605514771799712073114579083516153369898779898612291 | 99 |
UVM_INFO @ 9851071049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 39110704291611861101854964196266483812702401226342325989876211574320625714203 | 106 |
UVM_INFO @ 3415239382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 100179797976189134998220041585457155498706700838829489729611446519090181963332 | 115 |
UVM_INFO @ 6431376529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 17822177201707334464707096923046570801701084776937388879989227370902228881135 | 84 |
UVM_INFO @ 3886071021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13027540379903751004777150300256371698805781574639729370668600672986552132661 | 96 |
UVM_INFO @ 3386392455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 60475234908375503949061809076878697609629731409118469514187386755456307403332 | 122 |
UVM_INFO @ 20751382189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 69364250205189821248676168880406755292996775943216722208616074947650171705784 | 114 |
UVM_INFO @ 5661542905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 90326701020014193184079270289452850350992470176431252573212523994968954349984 | 87 |
UVM_INFO @ 1150325035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 98910006005209905920104494244446272558956159622176252431747470338420794752560 | 93 |
UVM_INFO @ 9321557361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 26903564983490404535825470707599371846578594739782718500528528470637010792266 | 96 |
UVM_INFO @ 2554929681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 110761614245628139462661088237414212182666871141272422646161441596468743754100 | 125 |
UVM_INFO @ 8346497662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 45985663873246666480011718336094707549755267599894875454883840565964246385259 | 186 |
UVM_INFO @ 146751992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 55826770416995207973901376480258253633946214239811657227646248747572980508151 | 198 |
UVM_INFO @ 98522134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 24264449733589601677770646169936729900240668375790610936516636386935644713976 | 162 |
UVM_INFO @ 721376656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 45088489865397940727412202001631248225718345701156571909007105364075976463130 | 192 |
UVM_INFO @ 187861893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 89354130540614943916075238395740707914475385617893441719063810742125584183916 | 188 |
UVM_INFO @ 1067177473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 52866234740523909740056998734792332291693059546216939774997891752217742988939 | 188 |
UVM_INFO @ 1543075240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 93904802336566890057095840308312369722599040660081826562891772940164479823782 | 108 |
UVM_INFO @ 1171659616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 29684039081204959217378061952692917432487271594422127211077776429319145609938 | 172 |
UVM_INFO @ 1439681538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 94475263932368265114409091774414301091850179592590252144300259141115299538030 | 176 |
UVM_INFO @ 916704332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 100166967276420326946058282247486261783805626480463594751203175821086843090038 | 182 |
UVM_INFO @ 172643935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 91057673654907770542873397865456034600775136502962252500163022885877686281073 | 128 |
UVM_INFO @ 101518421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 68582864058823894943466361654135845801505640780214510531741890064380370806159 | 192 |
UVM_INFO @ 278927447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 18320713791443116257383550771787416210457383798292269182668193702353353938216 | 200 |
UVM_INFO @ 375000466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 16354045666628962122088364741494043746562289633783638515629265248108211635001 | 198 |
UVM_INFO @ 179395922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 71092595118821669614008970686667418383453482667579006191438166722985420579844 | 154 |
UVM_INFO @ 305123877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 109905994276732113901749871808180516168445461233038417631562508486380402783009 | 150 |
UVM_INFO @ 404391754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 96276416500445760202318685514401104234377907237923622789673413380706692184767 | 182 |
UVM_INFO @ 1131161283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_entropy_stress | 23414853454710702325033308540581251016732952626661607265490343606776454865481 | 134 |
UVM_INFO @ 187861222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| alert_handler_entropy_stress | 43760860666353580843860113423092592991108437754886846497644147694984637730687 | 186 |
UVM_INFO @ 359016882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 71594793705666928148139248071166342570828477897409139291366510869487948283359 | 200 |
UVM_INFO @ 1599274575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 5 test runs | |||
| alert_handler_stress_all_with_rand_reset | 35694117720297317441105182613341486220611706249291805587601414237018406556195 | 84 |
UVM_INFO @ 498968587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 106208733058965087675837039723449931133470995674240497479958645642109504248969 | 112 |
UVM_INFO @ 1341630981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 90271793454661943702897256978329136960242840552637378707219271914952384526893 | 176 |
UVM_INFO @ 3063032687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 3164732877058205811762327947664478323332280597029263167202167175139850719748 | 108 |
UVM_INFO @ 847775246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 113129691964657865608214115011532418354663913761631826665940437625482562154955 | 92 |
UVM_INFO @ 870535563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 4 test runs | |||
| alert_handler_ping_timeout | 44574074530747526885259396689892144560871758416480061889012862324742910665810 | 80 |
UVM_INFO @ 607430515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 61012219765059001571883163720759342468194890163084750506612865522544844267177 | 80 |
UVM_INFO @ 496347494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78026473379423753809958116801360038752732471558627212032768194097969506511506 | 80 |
UVM_INFO @ 211575787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 33639756436112243732741847160533615360521956421370691138031739799345090636695 | 80 |
UVM_INFO @ 81899952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state | 2 test runs | |||
| alert_handler_stress_all | 74705194028493852453549071810398786808789143924607591231863915657819240441568 | 233 |
UVM_INFO @ 6896603679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_sig_int_fail | 69994324670623420190659603998239349116501446443979175708249170383559257579713 | 84 |
UVM_INFO @ 989293862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_stress_all | 73383591987709469637425723658874125862185109529771096853955248839375592224048 | 184 |
UVM_INFO @ 13087748917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt | 1 test run | |||
| alert_handler_lpg | 107434010380293027595730654667372219078856805964314648502536009468284426625258 | 83 |
UVM_INFO @ 126010860095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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