Simulation Results: clkmgr

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.87 %
  • code
  • 98.54 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.07 %
  • branch
  • 98.74 %
  • cond
  • 95.68 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
76.55%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.300s 55.405us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.190s 24.638us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 7.640s 887.009us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.410s 23.613us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.070s 165.110us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
clkmgr_csr_aliasing 1.410s 23.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.240s 37.446us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.620s 112.780us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.380s 86.288us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.140s 42.016us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.300s 55.405us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 20.500s 2242.373us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 18.140s 2293.540us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 20.500s 2242.373us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 57.770s 8547.095us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.320s 77.198us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 4.730s 1033.905us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 4.730s 1033.905us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.190s 24.638us 1 1 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
clkmgr_csr_aliasing 1.410s 23.613us 1 1 100.00
clkmgr_same_csr_outstanding 3.210s 529.981us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.190s 24.638us 1 1 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
clkmgr_csr_aliasing 1.410s 23.613us 1 1 100.00
clkmgr_same_csr_outstanding 3.210s 529.981us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 14 30 46.67
clkmgr_sec_cm 33.940s 10312.540us 0 5 0.00
clkmgr_tl_intg_err 68.870s 10027.065us 14 25 56.00
shadow_reg_update_error 9 20 45.00
clkmgr_shadow_reg_errors 928.170s 200000.000us 9 20 45.00
shadow_reg_read_clear_staged_value 9 20 45.00
clkmgr_shadow_reg_errors 928.170s 200000.000us 9 20 45.00
shadow_reg_storage_error 9 20 45.00
clkmgr_shadow_reg_errors 928.170s 200000.000us 9 20 45.00
shadowed_reset_glitch 9 20 45.00
clkmgr_shadow_reg_errors 928.170s 200000.000us 9 20 45.00
shadow_reg_update_error_with_csr_rw 14 20 70.00
clkmgr_shadow_reg_errors_with_csr_rw 929.220s 200000.000us 14 20 70.00
sec_cm_bus_integrity 14 25 56.00
clkmgr_tl_intg_err 68.870s 10027.065us 14 25 56.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 20.500s 2242.373us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 18.140s 2293.540us 10 10 100.00
sec_cm_meas_config_shadow 9 20 45.00
clkmgr_shadow_reg_errors 928.170s 200000.000us 9 20 45.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.600s 133.104us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.780s 160.990us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.380s 76.451us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 2.160s 285.692us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.470s 86.910us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 33.940s 10312.540us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.180s 41.877us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 33.940s 10312.540us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 9.170s 1167.036us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 111.150s 21489.685us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 13 test runs
clkmgr_shadow_reg_errors 45744529627084106479330307309808138690555839993548778281772382830740121738704 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 74754357271995423015241974760041916376434482011880481885227320053175281339376 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 42504928196756665501345894291677760614290703263010893484908098904417967442301 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 87357516236573538306422369324683265319360581035292567249172925430908527548253 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 13915371789422845468478508862661211425159765336106520050346028681777006073532 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 102243763733909393930576715579242168561763014374892499891854758883607890818136 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 33240637245832054805820129456566037897737387388089858737747596009321032857070 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 3203923646274585175525841589304914906618399501026623450669269110589358801318 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 114626971907607733167817652016726196029159946850284478351725551990556535566898 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 1642737556331356619543334850508361840642800453386214172607831661173417528545 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 90825715723271774375880781265877401105416047460306164271787472690732556127489 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 44313265923741485322348934478260998901650372517378611209820733925134108486012 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 83061866996717324021301082147358980163583584342730412387495210588551431016736 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 12 test runs
clkmgr_tl_intg_err 68393231847663561997010098994830082885141317263424787600378351629899631953590 96
UVM_INFO @ 10024471834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 19159795720464058283045823715420146016024452959192763917045524753300000041242 191
UVM_INFO @ 10312540087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 79632311332904346661095397487214735183087010845340841702880059651233610037785 107
UVM_INFO @ 10023151226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 5009763749133451590867884178327797124925106885671413224895519826608425827682 117
UVM_INFO @ 10027065277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 89868492453278364142758584169189867723306173089960178496904802662411508097074 136
UVM_INFO @ 10092737283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 115041483699484620086385775521368412705523130985793492711960524301311796242831 93
UVM_INFO @ 10020174733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 38530602574645907816298492735637648449305299465396970786355551253479891645646 113
UVM_INFO @ 10044099196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 27960789589599124586119725195954264525344137251417092203675034259278483624602 131
UVM_INFO @ 10080868307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 27601525567468975157952833700665868475921027383170460313071945305241031043393 219
UVM_INFO @ 10165861944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 112040942281387666576253857885462487593731788618161842168543434652011992851231 144
UVM_INFO @ 10061807862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 72228174072258982769523378398418526235466012293047832922599452216909269981827 192
UVM_INFO @ 10298707608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 60707343869120101331452932036088250026984334266360833262461325521998027340308 145
UVM_INFO @ 10180233094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 4 test runs
clkmgr_sec_cm 53621431247994608235201585866137528568793263399239790081598245411731506368525 89
UVM_INFO @ 18038316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 25419867245176707973309082788569911976598115354934271886226766225601745918274 81
UVM_INFO @ 4455330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 67234774922715781589142126360984033491653124152431106119060820069501474443636 96
UVM_INFO @ 31707918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 91379343812186319660398920046156275110647142884761745156095415716676994355569 80
UVM_INFO @ 9050943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*) 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 9274258843257444058213558024353775532239776731929990254975405718547278264824 75
UVM_INFO @ 2255561474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 4504268022907001171390120362219955591463529740021727577239574828080291692467 76
UVM_INFO @ 2582231158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 102504952432515141717951448955455941243768773816347706759082171707187758068438 74
UVM_INFO @ 52566190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 57131475550227919020428070678283504122646476744032517798500405782503090977763 75
UVM_INFO @ 2101185880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Check_csr_read_clear_staged_val task: check storage_err status 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 50522864374188906654978607505752490784183637261100606483201422029443591141454 75
UVM_INFO @ 44486205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---