Simulation Results: csrng

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.63 %
  • code
  • 96.20 %
  • assert
  • 96.72 %
  • func
  • 90.97 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.16%
V2S
99.22%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 10.000s 25.063us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 33.000s 87.624us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 31.000s 36.750us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 37.000s 324.043us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 34.000s 53.765us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 33.000s 22.901us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 31.000s 36.750us 5 5 100.00
csrng_csr_aliasing 34.000s 53.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
alerts 500 500 100.00
csrng_alert 48.000s 4175.482us 500 500 100.00
err 500 500 100.00
csrng_err 29.000s 26.079us 500 500 100.00
cmds 2 25 8.00
csrng_cmds 3600.000s 0.000us 2 25 8.00
life cycle 2 25 8.00
csrng_cmds 3600.000s 0.000us 2 25 8.00
stress_all 24 25 96.00
csrng_stress_all 603.000s 13664.035us 24 25 96.00
intr_test 10 10 100.00
csrng_intr_test 28.000s 30.890us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 34.000s 158.551us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 12.000s 200.417us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 12.000s 200.417us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 33.000s 87.624us 1 1 100.00
csrng_csr_rw 31.000s 36.750us 5 5 100.00
csrng_csr_aliasing 34.000s 53.765us 1 1 100.00
csrng_same_csr_outstanding 25.000s 114.498us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 33.000s 87.624us 1 1 100.00
csrng_csr_rw 31.000s 36.750us 5 5 100.00
csrng_csr_aliasing 34.000s 53.765us 1 1 100.00
csrng_same_csr_outstanding 25.000s 114.498us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
csrng_tl_intg_err 23.000s 662.053us 25 25 100.00
sec_cm_config_regwen 21 30 70.00
csrng_regwen 28.000s 22.233us 16 25 64.00
csrng_csr_rw 31.000s 36.750us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 48.000s 4175.482us 500 500 100.00
sec_cm_intersig_mubi 24 25 96.00
csrng_stress_all 603.000s 13664.035us 24 25 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 48.000s 4175.482us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
sec_cm_constants_lc_gated 24 25 96.00
csrng_stress_all 603.000s 13664.035us 24 25 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 48.000s 4175.482us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 23.000s 662.053us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
csrng_sec_cm 20.000s 81.368us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 32.000s 118.287us 200 200 100.00
csrng_err 29.000s 26.079us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 18 test runs
csrng_cmds 64830521122280107640249385008431683045315146331200946700036200540015482011964 100
UVM_INFO @ 327530514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 100595757947051858582033901269620253608902925573825479982509737991103496072126 100
UVM_INFO @ 186906122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110653077196076257094258708465259717679455146084686522352099187708076246173233 100
UVM_INFO @ 333768352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 29356387166937721535242134584620554115802129694063631070999663860174978795481 100
UVM_INFO @ 97699845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 48108117271469873506689900394766767446294810114792733728657552059282729966496 100
UVM_INFO @ 152956365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 78462804312723733005291562658481652365585352956850970018229550742225748028180 100
UVM_INFO @ 80309642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54431187429241857044607305789002635734581788158829763903011930571102391265431 100
UVM_INFO @ 283067704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 32997551013660066106855413103573263546350621815359816427462851268336972583130 100
UVM_INFO @ 25235906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 40456733141685349821421650803749280972025413354729502503675696707043069865193 100
UVM_INFO @ 25117533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 39530906411530463856303760050629962311250758451363810016084919566816236995864 100
UVM_INFO @ 48848309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 90869954256084574379622473360551482475867826964518471202407229302382480948736 100
UVM_INFO @ 32354027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 10418421228370124382298501739552306232554935325322023772442368148741189872744 100
UVM_INFO @ 51043620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 39582298448702870918444867761747456236070444402079107990607849905102117283076 100
UVM_INFO @ 57568601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 4639255061466019264264674056940852504894319467060054295068599991706926112271 100
UVM_INFO @ 58315932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 20416151820327364704428570344987338867826043233823674678266519746031245467023 100
UVM_INFO @ 9941171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96279400655276068937749618558440047899379759178076801027031879450095876135304 100
UVM_INFO @ 72108458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 7494018451889062826229759659019479928305314640603682515548258712565832964126 100
UVM_INFO @ 81183279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 113220447488514625767723979107065845999026714424561016958546530656070146639478 100
UVM_INFO @ 256393966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 8 test runs
csrng_stress_all_with_rand_reset 59760142415207818680508048645559751169235691220158154642155743391960798828796 None
csrng_stress_all_with_rand_reset 72567855896078731832975371721071611579122492831157159084555199147695734305377 None
csrng_stress_all_with_rand_reset 19278913126266381929983469971382161293162620207604060161875826338726890606851 None
csrng_stress_all_with_rand_reset 18448392223074272958596706333284225323990034144852807203621701333672335242650 None
csrng_stress_all_with_rand_reset 49413096809561667045156814040683545267599177816503810796192881054621711598272 None
csrng_stress_all_with_rand_reset 4035478403322092222312623277229381510238986481232794572009430283262405093034 None
csrng_stress_all_with_rand_reset 110280238543235978152060530395977154581078224124605927968647238938073494100313 None
csrng_cmds 45939996835092955345384250048667976108189335532410182543699982774573159314182 None
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 5 test runs
csrng_regwen 8571929128289588061631615663032612097252534504181770914206230065573741734621 99
UVM_INFO @ 9678528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 5519613159897495001943668057468729796570556180127367968139939941301949568550 99
UVM_INFO @ 10443906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 38315687374472513461814016337692749956529900866461194479707728475751515325030 99
UVM_INFO @ 62429792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 76208760060657989203289696335907691267586639176114569564494936471336094524353 99
UVM_INFO @ 5064563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 17959903802986748359556628610472191028409427673855477202230395446690288424991 99
UVM_INFO @ 2868538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 4 test runs
csrng_regwen 60855817354208425741221180053748271460827405300266254016091769539552761545550 99
UVM_INFO @ 1625553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 6488105774814725882144702044895813305170836308053202807824886667766568198918 99
UVM_INFO @ 9357296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 66922143245285983406884203754077551949026022018752026028121425479404889743543 99
UVM_INFO @ 1329791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 43121595550409401051426116574801532169077546937828317878487485631607321913490 99
UVM_INFO @ 3693529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all_with_rand_reset 8580436672035752715289282406049577702263290333120679788374129922391072224151 168
UVM_INFO @ 2293357626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 4416608885817572648598027801064511722406666310769637341129079752153789890746 112
UVM_INFO @ 61417542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 4283193856674659394184195136227896319319168627334523380173947290425350325155 221
UVM_INFO @ 32751392058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 2 test runs
csrng_cmds 74874344034558541554564491259032581085171087481033081405768492862045248291100 103
UVM_INFO @ 170859119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95245077488940141506417304844114785294690585737620801233273250604921349251747 103
UVM_INFO @ 160493186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [*] vs * [*]) 1 test run
csrng_stress_all_with_rand_reset 33290070924334140102016333842760522657088305311714581681767896700428858475896 135
UVM_INFO @ 3131471244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 102049580032923044474037863165690874795246836810075665620699590196764882013635 108
UVM_INFO @ 8232800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 59859840128701685947970980541794779735330410754158960986152416288751601151950 109
UVM_INFO @ 56563887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---