Simulation Results: edn/edn0

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.28 %
  • code
  • 95.58 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.02 %
  • toggle
  • 97.07 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
98.02%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.280s 18.058us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.110s 15.433us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.200s 132.969us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.910s 286.164us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.590s 27.899us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.580s 62.937us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.200s 132.969us 5 5 100.00
edn_csr_aliasing 1.590s 27.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 66.130s 4391.075us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 66.130s 4391.075us 100 100 100.00
genbits 100 100 100.00
edn_genbits 66.130s 4391.075us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.310s 23.488us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.980s 500.755us 200 200 100.00
errs 100 100 100.00
edn_err 1.640s 21.099us 100 100 100.00
disable 88 100 88.00
edn_disable 1.330s 14.060us 50 50 100.00
edn_disable_auto_req_mode 8.100s 500.000us 38 50 76.00
stress_all 30 30 100.00
edn_stress_all 8.950s 437.844us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.220s 40.287us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.320s 20.349us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.520s 236.021us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.520s 236.021us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.110s 15.433us 1 1 100.00
edn_csr_rw 1.200s 132.969us 5 5 100.00
edn_csr_aliasing 1.590s 27.899us 1 1 100.00
edn_same_csr_outstanding 1.480s 39.713us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.110s 15.433us 1 1 100.00
edn_csr_rw 1.200s 132.969us 5 5 100.00
edn_csr_aliasing 1.590s 27.899us 1 1 100.00
edn_same_csr_outstanding 1.480s 39.713us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 9.390s 757.442us 5 5 100.00
edn_tl_intg_err 6.220s 789.306us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.350s 18.348us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.980s 500.755us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.390s 757.442us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.390s 757.442us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.390s 757.442us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.390s 757.442us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.980s 500.755us 200 200 100.00
edn_sec_cm 9.390s 757.442us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.980s 500.755us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 6.220s 789.306us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 76.180s 7519.087us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 7 test runs
edn_disable_auto_req_mode 85087244804439354626600797606363268841439069911035354238530022160582420846246 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 48313202215024159128268413318367228599712675095321429980881516312135962638541 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 71648612687514264378146389224135292456228374747082018688300126516693434057573 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 28290410224564883067514001093067152693558579701846411139860647141713231046603 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 35974918518460561305581665725434647402198547259322237613757056304176030022549 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 19726559508251543443210489330734003041915911577686505027584218665117745808406 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 78141092653991967274049027273638899060201900792824926896955846730517232673338 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 5 test runs
edn_disable_auto_req_mode 83433730940392292639224106442743452662737553617709055009376620058182206754094 88
UVM_INFO @ 41781025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111784703727985036232407606155962513198826495530235524826733198383451528461978 88
UVM_INFO @ 35599975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72333541877898378697256383863273866491756499895524700144778931758622482346030 88
UVM_INFO @ 30248114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 103522857428186279170671208984846930629533972204527670013195985318253000895780 88
UVM_INFO @ 26039167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 73461045864909343023150022011187711170609689939804226263159947753564763791325 88
UVM_INFO @ 119399351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 57050557565403245272134043595313924833782613000176666359639526209927806398707 155
UVM_INFO @ 1816420972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 48190678526503136930030899779716948482506138515926751862747307252139829404618 229
UVM_INFO @ 2630324733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 42945331724658043277109137169685365204463683505345802566719832586578439625112 213
UVM_INFO @ 1806482104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 44568293270694511706087672528791460398867895418858388832997645695032656030502 309
UVM_INFO @ 1970976538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---