Simulation Results: edn/edn1

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 95.90 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.85 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.01%
V2S
99.57%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.080s 29.287us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.040s 28.410us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.070s 47.101us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.760s 91.122us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 53.462us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.270s 65.369us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.070s 47.101us 5 5 100.00
edn_csr_aliasing 1.140s 53.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.900s 272.921us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.900s 272.921us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.900s 272.921us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.510s 21.548us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.620s 224.940us 200 200 100.00
errs 100 100 100.00
edn_err 1.470s 29.198us 100 100 100.00
disable 94 100 94.00
edn_disable 1.190s 14.265us 50 50 100.00
edn_disable_auto_req_mode 6.670s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 8.670s 492.253us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.100s 21.326us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.480s 60.752us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 2.940s 129.031us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 2.940s 129.031us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.040s 28.410us 1 1 100.00
edn_csr_rw 1.070s 47.101us 5 5 100.00
edn_csr_aliasing 1.140s 53.462us 1 1 100.00
edn_same_csr_outstanding 1.600s 79.446us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.040s 28.410us 1 1 100.00
edn_csr_rw 1.070s 47.101us 5 5 100.00
edn_csr_aliasing 1.140s 53.462us 1 1 100.00
edn_same_csr_outstanding 1.600s 79.446us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 5.040s 1294.279us 5 5 100.00
edn_tl_intg_err 98.660s 10900.881us 24 25 96.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.210s 24.231us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.620s 224.940us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.040s 1294.279us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.040s 1294.279us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.040s 1294.279us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.040s 1294.279us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.620s 224.940us 200 200 100.00
edn_sec_cm 5.040s 1294.279us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.620s 224.940us 200 200 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
edn_tl_intg_err 98.660s 10900.881us 24 25 96.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 107.280s 6378.575us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 35803986472387928068089402678056856764754012559124163847779588243283431000424 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 74032225264962269595734480871971786514726590933167864011035600925203100710034 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 98491749645020239198738768916325239126197718700575256432886470331417552415061 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 22541329032241948565128936010754264405272179507942446854119337676688202816940 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 7032578629214368831200420866957735415479083148628069599528126861188092035660 220
UVM_INFO @ 1102684432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 72809331966443602050524795716795557691735257643918675329312989741700765706950 189
UVM_INFO @ 1731425984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46539564641279553719426966951355947993691085017093876597188452289623224729254 336
UVM_INFO @ 2728536427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *. 1 test run
edn_disable_auto_req_mode 71090927431235728648922870972050913075782559159996707185750335028940640850615 88
UVM_INFO @ 127826680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 106703226624867254106425609280046661166151908804728237136070561134037190811247 88
UVM_INFO @ 18874719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_tl_intg_err 69926701738306599207410149000503880970957784298972812233261198385595949703277 121
UVM_INFO @ 10900881065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---