Simulation Results: flash_ctrl

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.97 %
  • code
  • 95.50 %
  • assert
  • 97.02 %
  • func
  • 98.39 %
  • line
  • 96.10 %
  • branch
  • 97.45 %
  • cond
  • 94.85 %
  • toggle
  • 96.60 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
99.04%
V2S
98.53%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 130.200s 95.138us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 25.050s 29.076us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 24.520s 181.844us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 51.830s 3775.097us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 51.630s 2753.638us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 18.050s 64.369us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
flash_ctrl_csr_aliasing 51.630s 2753.638us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 12.360s 264.752us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 12.270s 24.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 25.140s 54.985us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 73.880s 114.303us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1606.280s 1155221.605us 3 3 100.00
flash_ctrl_hw_rma_reset 944.890s 760573.742us 20 20 100.00
flash_ctrl_lcmgr_intg 14.670s 81.397us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2229.670s 299789.654us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 265.550s 13546.576us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 160.960s 11925.215us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 2485.990s 109610.937us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 89.930s 711.153us 5 5 100.00
rd_buff_eviction_w_ecc 103 105 98.10
flash_ctrl_rw_evict 31.900s 48.057us 39 40 97.50
flash_ctrl_rw_evict_all_en 33.040s 31.929us 39 40 97.50
flash_ctrl_re_evict 36.550s 175.129us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 278.910s 17301.965us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 278.910s 17301.965us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 514.970s 14214.280us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 27.360s 562.490us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 1030.260s 1999.362us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 493.200s 1681.115us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 581.870s 959.003us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1350.920s 807.666us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 14.850s 25.808us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 158.270s 13333.088us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 24.440s 159.352us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 18.480s 161.350us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 567.480s 236.448us 5 5 100.00
secret_partition 130 130 100.00
flash_ctrl_hw_sec_otp 168.440s 29601.084us 50 50 100.00
flash_ctrl_otp_reset 119.860s 468.356us 80 80 100.00
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1606.280s 1155221.605us 3 3 100.00
interrupts 97 100 97.00
flash_ctrl_intr_rd 205.630s 33744.857us 38 40 95.00
flash_ctrl_intr_wr 3604.014s 0.000us 9 10 90.00
flash_ctrl_intr_rd_slow_flash 355.880s 26346.477us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 188.680s 37345.927us 10 10 100.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 74.900s 16164.504us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 58.370s 1361.663us 5 5 100.00
double_bit_err 34 35 97.14
flash_ctrl_read_word_sweep_derr 21.670s 217.350us 5 5 100.00
flash_ctrl_ro_derr 131.400s 4641.750us 10 10 100.00
flash_ctrl_rw_derr 172.650s 2102.874us 9 10 90.00
flash_ctrl_derr_detect 136.730s 1586.028us 5 5 100.00
flash_ctrl_integrity 464.510s 7986.819us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 24.560s 41.648us 5 5 100.00
flash_ctrl_ro_serr 123.200s 3993.325us 10 10 100.00
flash_ctrl_rw_serr 202.500s 34879.283us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 53.320s 1148.818us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 87.330s 1600.420us 5 5 100.00
scramble 59 62 95.16
flash_ctrl_wo 158.180s 3835.426us 20 20 100.00
flash_ctrl_write_word_sweep 13.260s 160.705us 1 1 100.00
flash_ctrl_read_word_sweep 8.500s 64.727us 1 1 100.00
flash_ctrl_ro 108.770s 2345.229us 19 20 95.00
flash_ctrl_rw 447.330s 20152.611us 18 20 90.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 31.840s 366.566us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 872.860s 75907.531us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 247.750s 10020.015us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 14.760s 135.546us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 13.670s 23.584us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 22.030s 227.611us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 22.030s 227.611us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 24.520s 181.844us 1 1 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
flash_ctrl_csr_aliasing 51.630s 2753.638us 1 1 100.00
flash_ctrl_same_csr_outstanding 26.290s 190.594us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 24.520s 181.844us 1 1 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
flash_ctrl_csr_aliasing 51.630s 2753.638us 1 1 100.00
flash_ctrl_same_csr_outstanding 26.290s 190.594us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 89.550s 574.684us 20 20 100.00
tl_intg_err 30 30 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
flash_ctrl_tl_intg_err 640.830s 3578.131us 25 25 100.00
sec_cm_reg_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 640.830s 3578.131us 25 25 100.00
sec_cm_host_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 640.830s 3578.131us 25 25 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 26.460s 160.598us 3 3 100.00
flash_ctrl_wr_intg 14.430s 91.024us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 130.200s 95.138us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 260 260 100.00
flash_ctrl_otp_reset 119.860s 468.356us 80 80 100.00
flash_ctrl_disable 24.440s 159.352us 50 50 100.00
flash_ctrl_sec_info_access 80.550s 9555.947us 50 50 100.00
flash_ctrl_connect 18.480s 161.350us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 14.340s 24.118us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 12.850s 69.664us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 78.590s 460.853us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 24.440s 159.352us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 26.460s 160.598us 3 3 100.00
flash_ctrl_access_after_disable 10.930s 77.700us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 28.700s 41.529us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 24.440s 159.352us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 27.360s 562.490us 10 10 100.00
sec_cm_mem_scramble 18 20 90.00
flash_ctrl_rw 447.330s 20152.611us 18 20 90.00
sec_cm_mem_integrity 24 25 96.00
flash_ctrl_rw_serr 202.500s 34879.283us 10 10 100.00
flash_ctrl_rw_derr 172.650s 2102.874us 9 10 90.00
flash_ctrl_integrity 464.510s 7986.819us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1606.280s 1155221.605us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 23.030s 834.305us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 3 5 60.00
flash_ctrl_phy_host_grant_err 13.460s 46.282us 3 5 60.00
sec_cm_phy_ack_ctrl_consistency 3 5 60.00
flash_ctrl_phy_ack_consistency 14.120s 41.629us 3 5 60.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2524.230s 5509.656us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 26.700s 897.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 374.250s 12044.725us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 3 test runs
flash_ctrl_rw 2493142089572532486364463820723567002493274726738706116765647949845896545746 108
UVM_INFO @ 1519504.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_ro 54280590307738033258235573544786369047918527294255717136118631572994988456833 108
UVM_INFO @ 126883.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw 69443823464762420964421394670188755306991165785780720423878933380168741639237 108
UVM_INFO @ 3598597.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 2 test runs
flash_ctrl_phy_host_grant_err 51836118230952863128779037784115108107646029063605537656174212770294700281385 125
UVM_ERROR @ 10546.8 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 10546.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 48990250966528981190314579925481176224116816370386995636035274549963170878 125
UVM_ERROR @ 23652.0 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 23652.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) 2 test runs
flash_ctrl_phy_ack_consistency 77682195035733876728684435304550228330753595205788889277696938033114559145876 109
UVM_INFO @ 13075.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_ack_consistency 3727381581275323213327906864646897885966519798642601226079862206436135360016 109
UVM_INFO @ 28484.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 2 test runs
flash_ctrl_rw_evict_all_en 70536299005998950555229760021386496151200830438958063356402588420326451599433 108
UVM_INFO @ 12457.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict 69671797729846077822678941856064382332872246128099537111891943089671945741413 108
UVM_INFO @ 25591.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
flash_ctrl_intr_wr 90482368722870330076162501344350901214847699213886717226191303743029390391285 None
UVM_ERROR (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface flash_ctrl_eflash_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
flash_ctrl_rw_derr 112707964753129108739467226883092704450943836502945661082754819121865564517187 108
TL item was: req: (cip_tl_seq_item@983547) { a_addr: 'hb4 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8f a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h8f d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 2024048.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp afd9d002_88337fbd:ffffffff_88337fbd mismatch!! 1 test run
flash_ctrl_intr_rd 81517872466794680403971361291373603928917285936614312137136265937609152498654 108
UVM_INFO @ 5821653.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp b820f588_75707b86:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 83272969017542712103342614256788538343194836021739573218207245354846231622835 108
UVM_INFO @ 33744857.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---