Simulation Results: gpio

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.78 %
  • code
  • 94.91 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 80.52 %
Validation stages
V1
100.00%
V2
94.27%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.710s 86.963us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.750s 109.734us 10 10 100.00
gpio_smoke_en_cdc_prim 2.020s 2260.317us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.910s 573.163us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 1.000s 209.036us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.980s 41.120us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 1.740s 172.232us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 0.900s 22.045us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.430s 23.525us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.980s 41.120us 5 5 100.00
gpio_csr_aliasing 0.900s 22.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.530s 627.250us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.770s 90.413us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.210s 144.504us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.950s 631.761us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 2.390s 94.180us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.260s 84.452us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 20.390s 3985.489us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 5.260s 507.282us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.370s 101.329us 10 10 100.00
stress_all 1 10 10.00
gpio_stress_all 72.110s 7304.550us 1 10 10.00
alert_test 10 10 100.00
gpio_alert_test 0.920s 32.841us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.980s 17.919us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 4.000s 751.576us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 4.000s 751.576us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.980s 41.120us 5 5 100.00
gpio_same_csr_outstanding 1.240s 150.503us 5 5 100.00
gpio_csr_aliasing 0.900s 22.045us 1 1 100.00
gpio_csr_hw_reset 1.000s 209.036us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.980s 41.120us 5 5 100.00
gpio_same_csr_outstanding 1.240s 150.503us 5 5 100.00
gpio_csr_aliasing 0.900s 22.045us 1 1 100.00
gpio_csr_hw_reset 1.000s 209.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.890s 1582.722us 25 25 100.00
gpio_sec_cm 1.360s 165.045us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.890s 1582.722us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 8 10 80.00
gpio_rand_straps 0.960s 24.264us 8 10 80.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 13.600s 764.268us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 11 test runs
gpio_stress_all 8152835249064800662884264711612845492963976998084985630448795740209469560886 1537
UVM_INFO @ 7304549855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 44882413119582996124465771609464378170152789744941439974499229930863104406873 704
UVM_INFO @ 1922250072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 40585444343880411123851705943391564268449897121113032711804744608020238973983 883
UVM_INFO @ 3076542243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 95721806166568572834517858285454419016522926668651470148453704100749833791694 1390
UVM_INFO @ 4310528093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 79731848979236895714080580526119509792771975788767165812994450195527122843606 75
UVM_INFO @ 1203482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 86854513671476354146136088054877017770694679627816658209937010591418536051242 76
UVM_INFO @ 19977634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 43694434181218145619943314658884897657764985487456825336199994970728728233063 603
UVM_INFO @ 1343998636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83047900190706967924113487013289954337426460595631593567853104526014617912677 647
UVM_INFO @ 4513623518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 32430961161445454328856155901580385176771316559158167304003054945367841561305 75
UVM_INFO @ 6023421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90236931018446713085963483825742310855782414566658739315555765879533435411962 1745
UVM_INFO @ 5292584320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 26633989139015587400854863639034946926360989249335101110196922204217843579566 1034
UVM_INFO @ 2912122995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 5 test runs
gpio_stress_all_with_rand_reset 41772796462559362221150348131193433235319519142302666490464147961172753474162 79
UVM_INFO @ 213255675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 104822193367280022490944457054245952882000381673071769221235042741459614369505 78
UVM_INFO @ 1298405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115624091312497391519410363544926347250879871925361417682231111475195986081168 78
UVM_INFO @ 551832749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115500002528468004632023175138118394132408431522477675502414740909330626205325 79
UVM_INFO @ 201488832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30909553054279472939344232058989681148524922995460940475413024245428813918935 216
UVM_INFO @ 116503410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 5 test runs
gpio_stress_all_with_rand_reset 72372310069767770858193042184555483243179183222253658740610376534987092583158 80
UVM_INFO @ 20770496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58815233428029253804537346442740805946239470033941144587614419853056671330189 80
UVM_INFO @ 6472273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 104806677963786372781831892977046386754820317086742492014248157519566267318165 308
UVM_INFO @ 764267670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 15211750773073079740587453884744808129799489708790712410115919441630469223414 80
UVM_INFO @ 3193886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 108450299627576221828159693709064698475179226268426662145719930738335623022924 268
UVM_INFO @ 1581918258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---