Simulation Results: hmac

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.84 %
  • code
  • 99.20 %
  • assert
  • 97.60 %
  • func
  • 99.73 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.020s 432.713us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.910s 33.177us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.140s 236.849us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.090s 2372.427us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.460s 111.882us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 490.610s 352066.422us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.140s 236.849us 5 5 100.00
hmac_csr_aliasing 4.460s 111.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 85.070s 7680.438us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 85.950s 40801.150us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 277.630s 22000.359us 30 30 100.00
hmac_test_sha384_vectors 557.190s 65557.830us 75 75 100.00
hmac_test_sha512_vectors 621.160s 154479.026us 75 75 100.00
hmac_test_hmac256_vectors 15.900s 499.307us 50 50 100.00
hmac_test_hmac384_vectors 18.070s 2214.275us 60 60 100.00
hmac_test_hmac512_vectors 20.050s 2129.513us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 37.720s 9357.712us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1428.730s 11841.502us 10 10 100.00
error 10 10 100.00
hmac_error 126.300s 185335.955us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 126.260s 12439.986us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.020s 432.713us 10 10 100.00
hmac_long_msg 85.070s 7680.438us 10 10 100.00
hmac_back_pressure 85.950s 40801.150us 25 25 100.00
hmac_datapath_stress 1428.730s 11841.502us 10 10 100.00
hmac_burst_wr 37.720s 9357.712us 50 50 100.00
hmac_stress_all 3497.930s 28279.830us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.020s 432.713us 10 10 100.00
hmac_long_msg 85.070s 7680.438us 10 10 100.00
hmac_back_pressure 85.950s 40801.150us 25 25 100.00
hmac_datapath_stress 1428.730s 11841.502us 10 10 100.00
hmac_wipe_secret 126.260s 12439.986us 10 10 100.00
hmac_test_sha256_vectors 277.630s 22000.359us 30 30 100.00
hmac_test_sha384_vectors 557.190s 65557.830us 75 75 100.00
hmac_test_sha512_vectors 621.160s 154479.026us 75 75 100.00
hmac_test_hmac256_vectors 15.900s 499.307us 50 50 100.00
hmac_test_hmac384_vectors 18.070s 2214.275us 60 60 100.00
hmac_test_hmac512_vectors 20.050s 2129.513us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.020s 432.713us 10 10 100.00
hmac_long_msg 85.070s 7680.438us 10 10 100.00
hmac_back_pressure 85.950s 40801.150us 25 25 100.00
hmac_datapath_stress 1428.730s 11841.502us 10 10 100.00
hmac_burst_wr 37.720s 9357.712us 50 50 100.00
hmac_error 126.300s 185335.955us 10 10 100.00
hmac_wipe_secret 126.260s 12439.986us 10 10 100.00
hmac_test_sha256_vectors 277.630s 22000.359us 30 30 100.00
hmac_test_sha384_vectors 557.190s 65557.830us 75 75 100.00
hmac_test_sha512_vectors 621.160s 154479.026us 75 75 100.00
hmac_test_hmac256_vectors 15.900s 499.307us 50 50 100.00
hmac_test_hmac384_vectors 18.070s 2214.275us 60 60 100.00
hmac_test_hmac512_vectors 20.050s 2129.513us 75 75 100.00
hmac_stress_all 3497.930s 28279.830us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3497.930s 28279.830us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.940s 50.766us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.930s 21.718us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.470s 223.928us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.470s 223.928us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.910s 33.177us 1 1 100.00
hmac_csr_rw 1.140s 236.849us 5 5 100.00
hmac_csr_aliasing 4.460s 111.882us 1 1 100.00
hmac_same_csr_outstanding 2.710s 268.816us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.910s 33.177us 1 1 100.00
hmac_csr_rw 1.140s 236.849us 5 5 100.00
hmac_csr_aliasing 4.460s 111.882us 1 1 100.00
hmac_same_csr_outstanding 2.710s 268.816us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.410s 99.156us 5 5 100.00
hmac_tl_intg_err 5.090s 1057.787us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.090s 1057.787us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.020s 432.713us 10 10 100.00
stress_reset 24 25 96.00
hmac_stress_reset 6.270s 10496.938us 24 25 96.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 938.100s 225900.349us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.120s 66.010us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [hmac_stress_reset_vseq] wait timeout occurred! 1 test run
hmac_stress_reset 315206588894111789254706323924219880346482595310224793000171461814631761806 229
UVM_INFO @ 10496937566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---