Simulation Results

Simulation Results: keymgr

18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.90 %

code
98.84 %

assert
97.72 %

func
91.13 %

line
99.20 %

branch
99.00 %

cond
98.08 %

toggle
97.90 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.59%
V2S		98.46%
V3		40.00%

73/73 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				30	30	100.00
	keymgr_smoke	18.160s	2998.775us	30	30	100.00
random				30	30	100.00
	keymgr_random	49.450s	13189.569us	30	30	100.00
csr_hw_reset				1	1	100.00
	keymgr_csr_hw_reset	1.230s	232.541us	1	1	100.00
csr_rw				5	5	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
csr_bit_bash				1	1	100.00
	keymgr_csr_bit_bash	13.350s	1241.307us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_csr_aliasing	6.470s	125.198us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	keymgr_csr_mem_rw_with_rand_reset	1.650s	98.520us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
	keymgr_csr_aliasing	6.470s	125.198us	1	1	100.00

421/427 passed

98.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				49	50	98.00
	keymgr_cfg_regwen	51.790s	5372.323us	49	50	98.00
sideload				80	80	100.00
	keymgr_sideload	24.880s	1704.971us	20	20	100.00
	keymgr_sideload_kmac	31.140s	3338.339us	20	20	100.00
	keymgr_sideload_aes	32.940s	2083.023us	20	20	100.00
	keymgr_sideload_otbn	5.890s	256.637us	20	20	100.00
direct_to_disabled_state				30	30	100.00
	keymgr_direct_to_disabled	18.100s	2390.292us	30	30	100.00
lc_disable				47	50	94.00
	keymgr_lc_disable	23.410s	5349.193us	47	50	94.00
kmac_error_response				19	20	95.00
	keymgr_kmac_rsp_err	17.360s	1379.333us	19	20	95.00
invalid_sw_input				20	20	100.00
	keymgr_sw_invalid_input	27.410s	5703.521us	20	20	100.00
invalid_hw_input				50	50	100.00
	keymgr_hwsw_invalid_input	49.730s	2194.785us	50	50	100.00
sync_async_fault_cross				20	20	100.00
	keymgr_sync_async_fault_cross	7.000s	461.067us	20	20	100.00
stress_all				49	50	98.00
	keymgr_stress_all	232.520s	14779.594us	49	50	98.00
intr_test				10	10	100.00
	keymgr_intr_test	1.140s	56.384us	10	10	100.00
alert_test				10	10	100.00
	keymgr_alert_test	1.180s	20.740us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	keymgr_tl_errors	4.840s	247.279us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	keymgr_tl_errors	4.840s	247.279us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	keymgr_csr_hw_reset	1.230s	232.541us	1	1	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
	keymgr_csr_aliasing	6.470s	125.198us	1	1	100.00
	keymgr_same_csr_outstanding	3.110s	118.632us	5	5	100.00
tl_d_partial_access				12	12	100.00
	keymgr_csr_hw_reset	1.230s	232.541us	1	1	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
	keymgr_csr_aliasing	6.470s	125.198us	1	1	100.00
	keymgr_same_csr_outstanding	3.110s	118.632us	5	5	100.00

V2S

320/325 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
tl_intg_err				30	30	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
	keymgr_tl_intg_err	9.110s	2385.713us	25	25	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	4.700s	422.373us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	4.700s	422.373us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	4.700s	422.373us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	4.700s	422.373us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	14.670s	1036.822us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_bus_integrity				25	25	100.00
	keymgr_tl_intg_err	9.110s	2385.713us	25	25	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	4.700s	422.373us	20	20	100.00
sec_cm_op_config_regwen				49	50	98.00
	keymgr_cfg_regwen	51.790s	5372.323us	49	50	98.00
sec_cm_reseed_config_regwen				35	35	100.00
	keymgr_random	49.450s	13189.569us	30	30	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
sec_cm_sw_binding_config_regwen				35	35	100.00
	keymgr_random	49.450s	13189.569us	30	30	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
sec_cm_max_key_ver_config_regwen				35	35	100.00
	keymgr_random	49.450s	13189.569us	30	30	100.00
	keymgr_csr_rw	1.830s	106.112us	5	5	100.00
sec_cm_lc_ctrl_intersig_mubi				47	50	94.00
	keymgr_lc_disable	23.410s	5349.193us	47	50	94.00
sec_cm_constants_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	49.730s	2194.785us	50	50	100.00
sec_cm_intersig_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	49.730s	2194.785us	50	50	100.00
sec_cm_hw_key_sw_noaccess				30	30	100.00
	keymgr_random	49.450s	13189.569us	30	30	100.00
sec_cm_output_keys_ctrl_redun				20	20	100.00
	keymgr_sideload_protect	9.550s	446.976us	20	20	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_ctrl_fsm_consistency				49	50	98.00
	keymgr_custom_cm	11.330s	891.291us	49	50	98.00
sec_cm_ctrl_fsm_global_esc				47	50	94.00
	keymgr_lc_disable	23.410s	5349.193us	47	50	94.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	11.330s	891.291us	49	50	98.00
sec_cm_kmac_if_done_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	11.330s	891.291us	49	50	98.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	11.330s	891.291us	49	50	98.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	10.860s	484.120us	5	5	100.00
sec_cm_ctrl_key_integrity				49	50	98.00
	keymgr_custom_cm	11.330s	891.291us	49	50	98.00

8/20 passed

40.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				8	20	40.00
	keymgr_stress_all_with_rand_reset	35.480s	4140.852us	8	20	40.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				12 test runs
	keymgr_stress_all_with_rand_reset	78053557371323928431141338142489941637643123220832667439135465674958500037427	107	UVM_INFO @ 110696089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	107814548577814938245138580998887897546354490725854755819686471068543222782953	182	UVM_INFO @ 122004491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	4838944053598634343118076806509278848293425135248511957323996504509398895925	588	UVM_INFO @ 1032665950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	2401683182293417319296117783438058284756411462522689222400388416455635874996	387	UVM_INFO @ 737848758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	22457134711346071811337420525541239774317936035460072997391978465299648028590	208	UVM_INFO @ 111355621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	64537793061165630245502200082958206689622601244346246432919611389597767058565	225	UVM_INFO @ 114657779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	3072556202827120613146178564748716921645297618715705909821515312415778828074	182	UVM_INFO @ 503588450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	112868806075077752386767712863092421807250298871926209804151362355448099371017	270	UVM_INFO @ 438582091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	108951550472534988612102288767863079639464132382908011242877569439565258762916	142	UVM_INFO @ 425297844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	58299824985903348852645692974236912719278323876475825526840211188645563439693	158	UVM_INFO @ 424516293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	107098699979975172509995950524443827067857901158745286631015673750476100652879	581	UVM_INFO @ 221493610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	65395578400927069543442955391817073897860867601208531767142373083184920086370	137	UVM_INFO @ 114823891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_operation_err triggered unexpectedly				1 test run
	keymgr_kmac_rsp_err	25412404417797559659469771917977546323129831144783298469964308014220553464666	311	UVM_INFO @ 72986777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[], act_key.key[]} !== keys_a_array[state][cdi][dest] (* [] vs [*]) KMAC key at state StCreatorRootKey for Sealing Kmac				1 test run
	keymgr_lc_disable	3190508984097962613723912819390983310209822131242413057123535472831825030065	268	UVM_INFO @ 268353015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share1_output_				1 test run
	keymgr_lc_disable	77683500961186894758505523309240766652883731358797409828188770243589236085840	163	UVM_INFO @ 123279551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*				1 test run
	keymgr_stress_all	56554331483171174281276672396412758949763004673885971975725075982481959620294	915	UVM_INFO @ 955826497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (keymgr_if.sv:380) [keymgr_if] timeout occurred!				1 test run
	keymgr_custom_cm	113232128246502251326709610140299741034816623382159123671573343774961593027846	107	UVM_INFO @ 205559292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[], act_key.key[]} !== keys_a_array[state][cdi][dest] (* [] vs [*]) AES key at state StOwnerIntKey for Attestation Aes				1 test run
	keymgr_lc_disable	100056397031665299106811409840463526210340832489492969411937993302516238708067	288	UVM_INFO @ 22308591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [] vs [*]) reg name: keymgr_reg_block.start				1 test run
	keymgr_cfg_regwen	94089379551865676088199238120605146540437863131505503074259659937236901278899	184	UVM_INFO @ 10943849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---