Simulation Results: lc_ctrl/volatile_unlock_disabled

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 86.09 %
  • assert
  • 94.69 %
  • func
  • 96.62 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.70 %
  • toggle
  • 88.33 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.100s 102.288us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.580s 23.295us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.440s 16.658us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.400s 66.750us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 28.774us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.640s 23.461us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.440s 16.658us 5 5 100.00
lc_ctrl_csr_aliasing 1.450s 28.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.970s 65.466us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.220s 1920.607us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.380s 14.784us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 5.630s 278.253us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 17.540s 8953.770us 19 20 95.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_prog_failure 5.630s 278.253us 20 20 100.00
lc_ctrl_errors 17.540s 8953.770us 19 20 95.00
lc_ctrl_security_escalation 18.890s 1194.105us 20 20 100.00
lc_ctrl_jtag_state_failure 74.070s 6421.730us 20 20 100.00
lc_ctrl_jtag_prog_failure 27.720s 2403.762us 20 20 100.00
lc_ctrl_jtag_errors 65.830s 12774.155us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 8.200s 444.292us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.180s 4136.324us 20 20 100.00
lc_ctrl_jtag_prog_failure 27.720s 2403.762us 20 20 100.00
lc_ctrl_jtag_errors 65.830s 12774.155us 20 20 100.00
lc_ctrl_jtag_access 17.650s 5917.753us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 31.440s 2100.615us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 5.040s 171.537us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.120s 141.461us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 25.050s 28125.251us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.540s 3662.493us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.300s 43.786us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.890s 914.794us 10 10 100.00
lc_ctrl_jtag_alert_test 2.350s 62.813us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 65.330s 13814.501us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.430s 13.462us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 237.570s 15082.166us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.570s 99.450us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.880s 1850.696us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.880s 1850.696us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.580s 23.295us 1 1 100.00
lc_ctrl_csr_rw 1.440s 16.658us 5 5 100.00
lc_ctrl_csr_aliasing 1.450s 28.774us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.870s 174.786us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.580s 23.295us 1 1 100.00
lc_ctrl_csr_rw 1.440s 16.658us 5 5 100.00
lc_ctrl_csr_aliasing 1.450s 28.774us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.870s 174.786us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
lc_ctrl_tl_intg_err 3.980s 1927.304us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.980s 1927.304us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.220s 1920.607us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 15.520s 379.949us 20 20 100.00
lc_ctrl_sec_cm 9.610s 123.822us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 18.890s 1194.105us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 7.970s 65.466us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.180s 4136.324us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.250s 836.627us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.250s 836.627us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 14.100s 6949.232us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.430s 1922.290us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.430s 1922.290us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 68.640s 24950.467us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 71641770100072646842991771573905681092233798515451677193043023073308983337013 169
UVM_INFO @ 10720770469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107298645995311310831719551571205437206398768774336605342844170437090735244195 150
UVM_INFO @ 108563492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63373837902839186453066375996293370758015036019962189790651341934034291560480 652
UVM_INFO @ 475074104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108486124265989635140280234739439974048728917340245081533980711265219565336159 594
UVM_INFO @ 483208440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 3216079450877318831786031642381135413012070885669158440515975537207687191288 1207
UVM_INFO @ 760829439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---