Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.51 %
  • code
  • 86.12 %
  • assert
  • 94.97 %
  • func
  • 96.44 %
  • line
  • 97.26 %
  • branch
  • 93.95 %
  • cond
  • 81.89 %
  • toggle
  • 88.33 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.030s 110.142us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.330s 123.929us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.410s 93.521us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.020s 439.859us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.570s 57.080us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.660s 90.057us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.410s 93.521us 5 5 100.00
lc_ctrl_csr_aliasing 1.570s 57.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.680s 95.340us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.790s 413.960us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.350s 23.860us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.870s 322.500us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 17.910s 599.325us 20 20 100.00
security_escalation 140 140 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_prog_failure 3.870s 322.500us 20 20 100.00
lc_ctrl_errors 17.910s 599.325us 20 20 100.00
lc_ctrl_security_escalation 9.900s 661.634us 20 20 100.00
lc_ctrl_jtag_state_failure 72.380s 56667.626us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.310s 687.254us 20 20 100.00
lc_ctrl_jtag_errors 82.990s 50409.078us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 13.110s 1486.177us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.290s 3604.679us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.310s 687.254us 20 20 100.00
lc_ctrl_jtag_errors 82.990s 50409.078us 20 20 100.00
lc_ctrl_jtag_access 14.880s 2794.795us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 18.630s 1209.624us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.090s 114.471us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.110s 246.859us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 16.590s 2399.736us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.480s 1040.088us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.500s 51.033us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.320s 792.932us 10 10 100.00
lc_ctrl_jtag_alert_test 2.390s 213.332us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 31.470s 3475.966us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.410s 19.907us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 227.550s 52538.655us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.440s 16.987us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.980s 1160.176us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.980s 1160.176us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.330s 123.929us 1 1 100.00
lc_ctrl_csr_rw 1.410s 93.521us 5 5 100.00
lc_ctrl_csr_aliasing 1.570s 57.080us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.110s 45.030us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.330s 123.929us 1 1 100.00
lc_ctrl_csr_rw 1.410s 93.521us 5 5 100.00
lc_ctrl_csr_aliasing 1.570s 57.080us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.110s 45.030us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
lc_ctrl_tl_intg_err 6.430s 3902.507us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 6.430s 3902.507us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.790s 413.960us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.170s 1460.030us 20 20 100.00
lc_ctrl_sec_cm 9.910s 133.337us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.900s 661.634us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 7.680s 95.340us 20 20 100.00
lc_ctrl_jtag_state_post_trans 26.290s 3604.679us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.820s 1877.223us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.820s 1877.223us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.620s 400.361us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 15.990s 3144.537us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 15.990s 3144.537us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 66.780s 44263.235us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 94917769312024470551643382775296426808166742343450944490530059183170415180788 16156
UVM_INFO @ 7782333390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30236298151095577308759905501083721187772891257929514691612577397250580469738 155
UVM_INFO @ 2016799731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113288331942770435759084654158120320619879310244982597177639093575450220413358 5220
UVM_INFO @ 2108441719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63100964976245695738847691624106444973683337420854924151220582943054044375049 475
UVM_INFO @ 20405154775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all_with_rand_reset 101377409430250490538878538712531162366589344404485628342208883221444194637246 1081
UVM_INFO @ 1504745918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---