Simulation Results: otp_ctrl

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.21 %
  • code
  • 85.99 %
  • assert
  • 95.40 %
  • func
  • 92.23 %
  • line
  • 90.33 %
  • branch
  • 86.85 %
  • cond
  • 94.05 %
  • toggle
  • 95.72 %
  • FSM
  • 63.02 %
Validation stages
V1
92.31%
V2
95.48%
V2S
95.45%
V3
22.77%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.510s 60.918us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.310s 143.571us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.180s 179.856us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.950s 555.551us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.920s 91.938us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.790s 146.362us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.180s 179.856us 5 5 100.00
otp_ctrl_csr_aliasing 3.920s 91.938us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.280s 79.166us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.600s 38.130us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 17.320s 3380.060us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.980s 2629.690us 300 300 100.00
partition_check 37 60 61.67
otp_ctrl_background_chks 21.380s 4323.381us 10 10 100.00
otp_ctrl_check_fail 26.520s 3307.590us 27 50 54.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 10.340s 885.138us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 27.540s 1718.886us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 15.420s 749.340us 10 10 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_dai_errors 23 25 92.00
otp_ctrl_dai_errs 52.140s 28703.715us 23 25 92.00
otp_macro_errors 3 10 30.00
otp_ctrl_macro_errs 21.210s 3347.080us 3 10 30.00
test_access 10 10 100.00
otp_ctrl_test_access 38.160s 8481.274us 10 10 100.00
stress_all 8 10 80.00
otp_ctrl_stress_all 158.440s 8663.935us 8 10 80.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.150s 157.318us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.180s 375.236us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 8.470s 2739.819us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 8.470s 2739.819us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.310s 143.571us 1 1 100.00
otp_ctrl_csr_rw 2.180s 179.856us 5 5 100.00
otp_ctrl_csr_aliasing 3.920s 91.938us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.760s 1711.204us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.310s 143.571us 1 1 100.00
otp_ctrl_csr_rw 2.180s 179.856us 5 5 100.00
otp_ctrl_csr_aliasing 3.920s 91.938us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.760s 1711.204us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
otp_ctrl_tl_intg_err 25.900s 4928.165us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 25.900s 4928.165us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
sec_cm_part_fsm_local_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_ctrl_macro_errs 21.210s 3347.080us 3 10 30.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
sec_cm_part_fsm_global_esc 203 210 96.67
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_ctrl_macro_errs 21.210s 3347.080us 3 10 30.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 34.200s 21555.575us 200 200 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.980s 2629.690us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 27 50 54.00
otp_ctrl_check_fail 26.520s 3307.590us 27 50 54.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 38.770s 8515.343us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 162.480s 38770.919us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 10.340s 885.138us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 27.050s 3358.667us 10 10 100.00
sec_cm_macro_mem_integrity 3 10 30.00
otp_ctrl_macro_errs 21.210s 3347.080us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.940s 3559.922us 1 1 100.00
stress_all_with_rand_reset 22 100 22.00
otp_ctrl_stress_all_with_rand_reset 124.540s 29297.579us 22 100 22.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 46 test runs
otp_ctrl_macro_errs 36627654852506595098371171479989703022268974354866477045699172545830284886584 1397
UVM_INFO @ 93855245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47563816212065061434866099723071314743555378622221576008033379253489546326772 4514
UVM_INFO @ 539243480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 90139106238256347647640702298104369564589386375116990831119511086151638268789 119828
UVM_INFO @ 8663934661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 95471401365425352049382225780956137029695111858551879979700306626854736513203 633
UVM_INFO @ 176704903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 87303229136620892198340810045909309634988101231932808796736836781717508281166 5831
UVM_INFO @ 1102328688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 13288489070204864139167094464841992321466760396778079494784144081697282210471 11041
UVM_INFO @ 2331524428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 4676149935283924106343737775351754324185008034377688239954698754748464149762 5346
UVM_INFO @ 1005548731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 73991879380016623231819990361359168198977783534786620636942551953716883646616 672
UVM_INFO @ 366437361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 40693013889710488109854946527360951455751999077842622863784308924544336428035 10504
UVM_INFO @ 1935793343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 103315709718975948489839776680611692339684844734090879118638382366778214073488 2864
UVM_INFO @ 865138477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 81342501109793083412968470969656916816913380669142494694801446452421513538957 1782
UVM_INFO @ 979141833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12864850970573899733047579684366725624728707224359976407084744159534622683590 11177
UVM_INFO @ 4848697228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 92981307116324758950281338801575333351596432414550215296612154700959037838411 1029
UVM_INFO @ 1641065195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 18921969191358933569588587750505883602862307751568081727305995428966629238894 353
UVM_INFO @ 165047768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 94465332185571887554681391333513056581975572646012111958556004388473621460898 5208
UVM_INFO @ 219148717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 3605561837987712342160289300804482863935509834704524406799152062598940741650 2967
UVM_INFO @ 1093404892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 61785109622784437450813513573755994287054290272493490997222954303652621628455 2953
UVM_INFO @ 2808101147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 24785707932983307335923977815067228983054113482238656416860204923367255036789 8235
UVM_INFO @ 2973186853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 11754820538433491827220497285005817963587517862555048631728636899402391368746 4159
UVM_INFO @ 7060284872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93649818759547415169259692917148485910880286787693782349567072109247339130168 8507
UVM_INFO @ 2837301806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 62477777328481161893032335256325527656768797193568949633702215638966969011880 2954
UVM_INFO @ 158720417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64839071357337106738674064827499718954837442761586054678292751146978438694537 2075
UVM_INFO @ 980578443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 97807433673795974630262319998668007782070227284003712587901454881277366959549 3944
UVM_INFO @ 1487355028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 59298656391012853678088385868447867111100284889762717606753351154197020360661 2438
UVM_INFO @ 153894060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 44024855812505550829333970007248945132485188194594891609440236942250592265652 4883
UVM_INFO @ 470962981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104423489608146190025339821134544123688332068134776776874475631854511352393692 153
UVM_INFO @ 35211912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54877381049594830653309073001153843929388881867611723318429349288040272283593 6714
UVM_INFO @ 873498049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45275881142358113309206432930964933439983875783314691879176318408955010014164 115
UVM_INFO @ 54156172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103998861550950336274382754172079339373830687211526628663078877549288585481199 2656
UVM_INFO @ 7366671570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 112675654298201980634858675507357477393473126263343078115081917776780594089773 3544
UVM_INFO @ 2104166703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77031118466938180405780767582494456273896401719262623824959018904624517512826 65773
UVM_INFO @ 2088695250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88850978346163888921020030323929128253366164201112024633639521878615081924592 2547
UVM_INFO @ 4021418923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 29179202912002232686054130699770355891746184882454975475407964293605866413016 5982
UVM_INFO @ 560078747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38301075556111123106047523310347305743222205280603028056322433919326765114273 2402
UVM_INFO @ 273257023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100093763471936931357524456138450957697491146064233157527456670140683070850624 10182
UVM_INFO @ 373445391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56264241779975523401409920176128234314749760043558866860787153019388001877492 3216
UVM_INFO @ 277123246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 71774033812549436975595282644052608449004275162174069087068478053911045087217 7194
UVM_INFO @ 932516889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 91263592681806079136422093375896965919908829989627779274788762415841558580652 5987
UVM_INFO @ 1130228325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 22598952503106295318993164726812636423561194797108933831670661399105582431805 3444
UVM_INFO @ 332780754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72144735463846019185657241415697270261035508768591348270030496090881018196697 11748
UVM_INFO @ 592424327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115031382781197690952912334697791821389304078203385551967886234922955626724690 33361
UVM_INFO @ 25350674028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110624188150987169022524075872706659478288659446104183364321093439876635537942 147
UVM_INFO @ 581623367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6031240031296856300024222424576718707776497159298109352445024457186191161594 30744
UVM_INFO @ 7154983311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77479500172036811862874077747388587029535531143116383707064474395905189239911 7977
UVM_INFO @ 653003209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33145809520966265465892144150829848152354921310706864090881517867592772713189 1206
UVM_INFO @ 6519721183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104555630722969992943509202936996313264107007893199859876413532241218431778339 4681
UVM_INFO @ 7485831580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 22 test runs
otp_ctrl_stress_all_with_rand_reset 7030757089140279883776030525093601265011153785280026925193824411562100796057 2360
UVM_INFO @ 6655020877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5604628812870151226292431831404159987779341400158511815803748418506430805288 7395
UVM_INFO @ 21091812223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16740362568150386755067259714667154083141508857946069939497737509821992155926 505
UVM_INFO @ 317479215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43328291013261076140306575393800098153383691874666618195359172847403426798598 3592
UVM_INFO @ 1734869435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9188768196928980947322904660807102055597101685380605509529709730665455971779 6091
UVM_INFO @ 4063738049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84529103593336509428604222497188024938295385209265880975317436370673329141672 15940
UVM_INFO @ 7716393502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112774829524743509604456829157230548137433514796782135109688538019286056999110 13529
UVM_INFO @ 1847260349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101247714573119518981418012345357206588781969032536066348595939731803062408007 5671
UVM_INFO @ 1481542114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71892540080174097799315397074620784368792026386695726618827094035556863079557 5248
UVM_INFO @ 1568088970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44625705185034019140952947700602197950220567889054610089080668527488279109755 589
UVM_INFO @ 146673973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95145699016684437791853461824266506095511088338086429311771675996145270487108 193
UVM_INFO @ 156217881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61985508235417926218982983287214373122088003537626558795210767931376708595637 13239
UVM_INFO @ 6062778858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83768164998933655632569775050390276759959994713141789200986234796892092524180 207
UVM_INFO @ 13952920232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52023947401436327917576121043730029340278456187607618679302911832379335201884 18090
UVM_INFO @ 24602557180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96356166323496469633086823524023781468416192663185705529394028322266192947617 5898
UVM_INFO @ 4972616356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104921731979531297254756268891985810086346854712336668073026836657580235835625 25602
UVM_INFO @ 11083834552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22763620685335589218209518449124346289142374171025407596896533416772747146578 2874
UVM_INFO @ 771332808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63237421204191522426521654344610847674272036394277866252240211381769716123593 155
UVM_INFO @ 77704498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86293953942837402902981140413406777041480470543516892667239117484183438836812 32203
UVM_INFO @ 8470040480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36736113819888085664503926799285225554943010048849493845994122670794474255780 9496
UVM_INFO @ 1366398455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99075804608541478708878813525767203301983658640958354380152641972342823128737 3242
UVM_INFO @ 14205690785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47821948866004584983296662182065878089841522930977317337210979597643881814190 3636
UVM_INFO @ 547843319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 22 test runs
otp_ctrl_stress_all_with_rand_reset 80548124016899815416060368070284471590294082623378879083102296854702507171064 93
UVM_INFO @ 107342019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73131715622976577289598007097934676516493746916610713920704051977300084971187 92
UVM_INFO @ 30135375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114971019368323460861715761896559659806383235734913970411038141522919686652316 24143
UVM_INFO @ 2156336051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43323146442694249454712387864848022623547153239502742952616874448698018545203 1775
UVM_INFO @ 3213381895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99754575432656786899601875399167936629208446952883464496408810884462934868606 24030
UVM_INFO @ 5902690399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64598172831929081461523034888032803299868730818110883381816125679751186758474 37136
UVM_INFO @ 3961580916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101484912014544331143254993046808071564230506181249556529994141032615227271870 241
UVM_INFO @ 6382687046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56446769841642812992670139859995095801547489983509928329056921956325059733470 16335
UVM_INFO @ 3701684521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28256391002183942580822781560809673539209345242596647032798083102117796614302 92
UVM_INFO @ 27622142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68037866430972327630064858258990823419303119688082798689144165356487901794257 19177
UVM_INFO @ 3479659592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70465820876557209155863238245419119102266178227957364977470794377313819260959 44251
UVM_INFO @ 4292859060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72378844032057876996149514097659263478939203819903749974458872892294958495915 92
UVM_INFO @ 26407606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15345417565946394777329343667655498371303984217827098964405822059909978895585 92
UVM_INFO @ 37930105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9321603939321740604060241060415680077004041739652939928902514101434830332192 41791
UVM_INFO @ 1246540588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55385840260182405420700999989364433241081225072625201688246486741302273403842 92
UVM_INFO @ 52209620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18650420826739149237458680026514788071383650200348252688297397817263603484271 30824
UVM_INFO @ 9075767418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15335229449290320220110981352886929777594540357746154107789124943255366603345 4097
UVM_INFO @ 357011989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9420247147385633146923026624190720396021292471373430706711433379062956960933 23896
UVM_INFO @ 4133767364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65514515790826072088564212626596844202140782212698542744717558322708985560215 92
UVM_INFO @ 427831542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27521587647445330741974041304920198386873049243949913698234369632908665819480 38115
UVM_INFO @ 2399158860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12267097840368936553998555055263098984716809716503988621686154314848171500699 9593
UVM_INFO @ 710531466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78369050143732606042949843778542909377895828893224110260595675764754742470137 4688
UVM_INFO @ 688281158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 17 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 109767623623480156687132629997850194297725435385156897678873751543339076351458 98
UVM_INFO @ 56682412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 99318526503168169777829345718981721608762268277620299607814097620515726393220 98
UVM_INFO @ 61384528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74618768901573294183517179526471256757532420047514919542646209442355734670741 12083
UVM_INFO @ 4560352741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22943065283379183773177279954453855741066124382073017372883023541308441269371 144
UVM_INFO @ 111539078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36451371667591682634629038055595181732252777913720129862101633731284949363722 3391
UVM_INFO @ 1046782295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47824211792632161613873960902358582404583823625326373676478190418093979820832 92
UVM_INFO @ 428986230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69924948331291927264935909147739631194245191328027009216111146962948813345228 92
UVM_INFO @ 53646609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32363119660407040411340324983000460815001106426580670977104488325670237842328 93
UVM_INFO @ 432668629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13059919868153461178029879078243873780690296815536949313718977573763414139240 93
UVM_INFO @ 47341327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99451886068435290950418687949049904151652751906656190852288063987708509269219 4557
UVM_INFO @ 4832386799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65169989662713446236825592478596649824235745858326769433615987583824239693409 13725
UVM_INFO @ 19026562865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91438932327711707660217995804423754577904334971433486716451079984709676965822 4124
UVM_INFO @ 14474016399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6594659996685545036879845478748417522967284906135040598476241452085852787065 21804
UVM_INFO @ 8183044901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20752032991193402122592877183221171161171353506306949272074609122897792972048 92
UVM_INFO @ 36145623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87043693160477555143173751228618938293120285400732233315620515986762393226143 3587
UVM_INFO @ 6319594484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81534301732048443778724724043031972045587742694225994399669728421496929998599 92
UVM_INFO @ 103294692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89607613196757535046636043324328485652227778354340356912604388032430920662205 92
UVM_INFO @ 53469777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 2 test runs
otp_ctrl_stress_all_with_rand_reset 67482690581987316845368448727356552951846082034311080757914594764779143981600 1613
UVM_INFO @ 10717503531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64283967057774753690583169360334736837916783409980534952189673789863995556415 110
UVM_INFO @ 10064678525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 2 test runs
otp_ctrl_stress_all_with_rand_reset 41087728106910834877426497737379484320944413579405515985870897669583047464451 466
UVM_INFO @ 11790075753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104642258181385063639942466857430797688974616606063470942349007814983270753493 94
UVM_INFO @ 3409524376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 73054796426968225569211112625468614907218045584896704466629436383454059529524 9205
UVM_ERROR @ 9686976458 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 9686976458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 111153104424723068028458510460725191332411482500359305014402194683434427792867 2451
UVM_INFO @ 457704034 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 457728726 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 458136144 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 458271950 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *b* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 62357453941125313706576930787441216573675987790215877199572973386941291682582 1998
UVM_INFO @ 21121741242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---