Simulation Results: pwrmgr

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.50 %
  • code
  • 97.54 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
89.05%
V2S
100.00%
V3
65.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.880s 26.914us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.790s 25.241us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.820s 27.568us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.950s 1709.457us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.130s 26.590us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.990s 120.390us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.820s 27.568us 5 5 100.00
pwrmgr_csr_aliasing 1.130s 26.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.040s 261.594us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.040s 261.594us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.060s 24.890us 10 10 100.00
pwrmgr_lowpower_invalid 0.810s 46.590us 10 10 100.00
reset 13 20 65.00
pwrmgr_reset 2.300s 1000.000us 7 10 70.00
pwrmgr_reset_invalid 0.950s 165.040us 6 10 60.00
main_power_glitch_reset 7 10 70.00
pwrmgr_reset 2.300s 1000.000us 7 10 70.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.280s 345.438us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.100s 146.850us 10 10 100.00
disable_rom_integrity_check 4 10 40.00
pwrmgr_disable_rom_integrity_check 2.810s 1000.000us 4 10 40.00
stress_all 8 10 80.00
pwrmgr_stress_all 6.360s 11559.312us 8 10 80.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.820s 33.406us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.480s 603.047us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.480s 603.047us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.790s 25.241us 1 1 100.00
pwrmgr_csr_rw 0.820s 27.568us 5 5 100.00
pwrmgr_csr_aliasing 1.130s 26.590us 1 1 100.00
pwrmgr_same_csr_outstanding 0.990s 21.451us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.790s 25.241us 1 1 100.00
pwrmgr_csr_rw 0.820s 27.568us 5 5 100.00
pwrmgr_csr_aliasing 1.130s 26.590us 1 1 100.00
pwrmgr_same_csr_outstanding 0.990s 21.451us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.660s 1383.114us 25 25 100.00
pwrmgr_sec_cm 1.550s 758.491us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.550s 758.491us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.550s 758.491us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.660s 1383.114us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.390s 827.708us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.280s 345.438us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.240s 824.355us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.070s 321.687us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.780s 40.726us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.550s 758.491us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.550s 758.491us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.550s 758.491us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.800s 45.309us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.800s 56.903us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.180s 301.098us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.820s 27.568us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.820s 27.568us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 4 10 40.00
pwrmgr_escalation_timeout 0.970s 676.345us 4 10 40.00
stress_all_with_rand_reset 9 10 90.00
pwrmgr_stress_all_with_rand_reset 13.050s 12823.863us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
pwrmgr_disable_rom_integrity_check 58480404377496255493478635251497189388372050970597812162782120742408001510986 94
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 38212643076507589466952943596760766856731659811374182756979815819358287846720 135
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 6131019336816062084769736067968903854818007471106675640286956548508439114047 109
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 88691960766488340804403504013198962169608993571849708399552323462343687278260 139
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 15443205998712588333695876493180473006580578497510518597565659398269194600824 84
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 42959611857746566470949369690927684498358276438385276288154739676560272541239 104
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 101953271589813479026552265083014915530323257276454250064843780926460991039314 164
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 80946007803944157693431434434097618220511703899143642131619302000815239091070 84
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 101447769497739707283168261641817905040724439261727365877252684066148407571538 125
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 6 test runs
pwrmgr_escalation_timeout 41745481872160894292760958023569788554947738863712704937686223468521917769719 79
UVM_ERROR @ 354923785 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 354923785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 15705962249109748807503731481471656777804824848720079209675187062154174175394 79
UVM_ERROR @ 491822831 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 491822831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 34870693561723384044423483046298563324337563599889941560137873216719512560525 79
UVM_ERROR @ 551649526 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 551649526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 66692056803745554630382957018962000010124088036811675157720363425273514073665 79
UVM_ERROR @ 676344804 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 676344804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 35570785529326662035426755660189435266979831967321992749393653843316405127978 79
UVM_ERROR @ 214137181 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 214137181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 67481848989406487207310492931239666541890275820628855167196165485305081926502 79
UVM_ERROR @ 97778124 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 97778124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 2 test runs
pwrmgr_stress_all 101102709957140360831922218735646505900310180751267991748485608590726212433199 451
UVM_INFO @ 11559311859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 110953599936371870665595085744239387485120188964328195793367277860169243120042 153
UVM_INFO @ 10093189370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp 2 test runs
pwrmgr_reset_invalid 21306088877653463366264994902839093821161887287945798679967600861547644616815 89
UVM_INFO @ 123715669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset_invalid 2693454047670210434018595644144395626316996324027847678112201784436235690630 128
UVM_INFO @ 108561921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
pwrmgr_stress_all_with_rand_reset 110944700222238094190440755889394550852513189704335955840539504378114537189971 509
UVM_INFO @ 589062625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks 1 test run
pwrmgr_reset_invalid 91194674367217605263151086137879133548686594124917889519862947771896063830480 90
UVM_INFO @ 27296562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitRomCheck 1 test run
pwrmgr_reset_invalid 7055213995335093040162551486955893435774011288759412775198788405525673196684 146
UVM_INFO @ 105923935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---