Simulation Results: rom_ctrl/32kb

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.48 %
  • code
  • 98.63 %
  • assert
  • 97.53 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.37 %
  • toggle
  • 95.33 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.740s 181.348us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.430s 186.533us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.290s 127.282us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.890s 168.556us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.480s 557.550us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.530s 176.715us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.290s 127.282us 5 5 100.00
rom_ctrl_csr_aliasing 4.480s 557.550us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.530s 286.760us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.900s 176.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 5.940s 346.274us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 27.280s 15313.398us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.030s 559.026us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.370s 127.769us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 10.370s 165.022us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 10.370s 165.022us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 8.430s 186.533us 1 1 100.00
rom_ctrl_csr_rw 5.290s 127.282us 5 5 100.00
rom_ctrl_csr_aliasing 4.480s 557.550us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.650s 127.648us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 8.430s 186.533us 1 1 100.00
rom_ctrl_csr_rw 5.290s 127.282us 5 5 100.00
rom_ctrl_csr_aliasing 4.480s 557.550us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.650s 127.648us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.160s 12517.579us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 292.840s 493.831us 5 5 100.00
rom_ctrl_tl_intg_err 63.750s 365.133us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 292.840s 493.831us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 292.840s 493.831us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 292.840s 493.831us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 292.840s 493.831us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.740s 181.348us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.740s 181.348us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.740s 181.348us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 63.750s 365.133us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
rom_ctrl_kmac_err_chk 9.030s 559.026us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 122.860s 2848.535us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.160s 12517.579us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 292.840s 493.831us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 396.080s 16228.393us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 60417178620807430918939176422151834056234725045433226803664730163413706609646 79
UVM_INFO @ 498572032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 75378635644926283030788860814057499065133758153282186153828714614208460359103 79
UVM_INFO @ 346274035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 77575997168640208313284625417271011362101972866956290659953346236776430600301 99
UVM_INFO @ 778976249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---