Simulation Results: rom_ctrl/64kb

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.48 %
  • code
  • 98.72 %
  • assert
  • 97.68 %
  • func
  • 99.05 %
  • line
  • 99.46 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 95.34 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 14.080s 304.545us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.950s 716.403us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 10.620s 515.918us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.320s 205.505us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.470s 955.603us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.400s 1955.370us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 10.620s 515.918us 5 5 100.00
rom_ctrl_csr_aliasing 9.470s 955.603us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 11.130s 292.563us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 9.350s 207.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 8.920s 1452.981us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 46.980s 4612.420us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.210s 421.276us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 11.450s 298.109us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 15.300s 2050.000us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 15.300s 2050.000us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 10.950s 716.403us 1 1 100.00
rom_ctrl_csr_rw 10.620s 515.918us 5 5 100.00
rom_ctrl_csr_aliasing 9.470s 955.603us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.690s 296.539us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 10.950s 716.403us 1 1 100.00
rom_ctrl_csr_rw 10.620s 515.918us 5 5 100.00
rom_ctrl_csr_aliasing 9.470s 955.603us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.690s 296.539us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.530s 1587.940us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 588.540s 2030.623us 5 5 100.00
rom_ctrl_tl_intg_err 140.320s 670.905us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 588.540s 2030.623us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 588.540s 2030.623us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 588.540s 2030.623us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 588.540s 2030.623us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 14.080s 304.545us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 14.080s 304.545us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 14.080s 304.545us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 140.320s 670.905us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
rom_ctrl_kmac_err_chk 16.210s 421.276us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 233.990s 18139.769us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.530s 1587.940us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 588.540s 2030.623us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 378.150s 5633.521us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 99570924303172858530172913739222745463671961352670334559680371580109908750554 79
UVM_INFO @ 1452981491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 19730979637027402426076631867658942228242018510496529689098870762947110484028 79
UVM_INFO @ 320685525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---