| V1 |
|
100.00% |
| V2 |
|
85.04% |
| V2S |
|
100.00% |
| V3 |
|
42.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.950s | 854.434us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.930s | 57.252us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.820s | 15.040us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.910s | 377.163us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.120s | 125.940us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.290s | 28.879us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.820s | 15.040us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.120s | 125.940us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 4.140s | 18236.093us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.380s | 2421.149us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 272.730s | 846069.487us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 272.730s | 846069.487us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 6.840s | 3824.700us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.900s | 17.133us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.870s | 43.597us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.540s | 525.201us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 2.540s | 525.201us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.930s | 57.252us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.820s | 15.040us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.120s | 125.940us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.150s | 41.308us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.930s | 57.252us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.820s | 15.040us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.120s | 125.940us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.150s | 41.308us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.200s | 89.924us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.560s | 148.906us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.560s | 148.906us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 10 | 10.00 | |||
| rv_timer_min | 1.860s | 204.193us | 1 | 10 | 10.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.380s | 43.414us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 16 | 20 | 80.00 | |||
| rv_timer_stress_all_with_rand_reset | 40.410s | 16661.084us | 16 | 20 | 80.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 28 test runs | |||
| rv_timer_min | 53252005087755903423656856059686196870503384754649990866993300862925114885508 | 77 |
UVM_INFO @ 204193181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80056012302208371694796812314792562423026679871638723156722129876124616220622 | 75 |
UVM_INFO @ 108188566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 93598004121947846845769213676529380932890992554843047194332561854155811808565 | 75 |
UVM_INFO @ 507405021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 113189603541759784183940765638192204570411452207343801069013501228867419362020 | 77 |
UVM_INFO @ 86245947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 71046797096375686412401357749885276328679485754487848611661249486437419332207 | 75 |
UVM_INFO @ 706451588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 50951162781212039500205441006747617120728585459412598085324480690252359742990 | 75 |
UVM_INFO @ 228148377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 104026063660423080768182694281997552207883502694584010552813957307055369521633 | 75 |
UVM_INFO @ 84232171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 34815937364922744173331963795999971997643211591009620915194067005222697990964 | 77 |
UVM_INFO @ 261948445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80055672004109707436649137224772674969765618516536118570352922326807649839115 | 77 |
UVM_INFO @ 116949097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 12567686839457471865688503299327595584917738019257441731324273451862273942822 | 75 |
UVM_INFO @ 2373421552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 96377320618058835250472215032197425188802225037341437128555685904566877344367 | 75 |
UVM_INFO @ 291137823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 33619840753759192013073073306509135425731047193017280725475487899733705319968 | 76 |
UVM_INFO @ 55340850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 64274171230444520596738406120395828291855635024052131853004083970745994156603 | 75 |
UVM_INFO @ 709594011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 57959266991370710794551473788317305101351988218563027590567370362824516953500 | 75 |
UVM_INFO @ 61007835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 46521791064749045413295879432565482199648713107255526529492037686132961954530 | 75 |
UVM_INFO @ 549772601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 57618892312538730838018845235926317318731853684276151597955370700456252453294 | 78 |
UVM_INFO @ 65163983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 39575919157612527269492113465253813770846088818593424085528008859114653369621 | 75 |
UVM_INFO @ 231320432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 106944772440287035568353879824876906918707990362995467424560932019192706116171 | 80 |
UVM_INFO @ 77148570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 53089099547701625932277001520127122209681675613328867543883956053657804682115 | 75 |
UVM_INFO @ 60023205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 60136808929063439791966507624383651920395779838226668663543035468083595013844 | 75 |
UVM_INFO @ 284579990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 49654402438681316337287324978095977728497699797304876178621141310708044053997 | 76 |
UVM_INFO @ 18236093490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28352166031227991252100465533927326926408607565259005275535541860500373524427 | 75 |
UVM_INFO @ 286248080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 84510798598032109306397274972896079922863724751465074092591103102280321178680 | 75 |
UVM_INFO @ 73129078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 57127464635972464038408603217502450030654829604895857601753952496444793987252 | 75 |
UVM_INFO @ 332080840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85314011770132838377659489629514560103735320553959759559212561133832896269183 | 75 |
UVM_INFO @ 262758274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 91084907813278006014714357673197603185341717064203342546553925507787148437947 | 75 |
UVM_INFO @ 89094925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 55878244558129681051017133425398584063900986160926195510572794933693242726576 | 76 |
UVM_INFO @ 261891619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 31522865479631354730649124430770683778903639604656895057219373487027197412737 | 75 |
UVM_INFO @ 100567120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| rv_timer_max | 38409880439432818115228422884542029687023089734735995770729890482040716643830 | 75 |
UVM_INFO @ 847288726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 37614864038793814438760577913281970572854393952399494524051568223394000668573 | 75 |
UVM_INFO @ 177333134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 111901261210391847158383417849051899580692031023590594221238060916907682907728 | 76 |
UVM_INFO @ 555772041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 1595188443594227824298068134806764781908347870901173576041245803461476394187 | 76 |
UVM_INFO @ 708833932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 112866813582475268207327640882513845427030646142616761495608273614932551603336 | 75 |
UVM_INFO @ 88428731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 79639152598778860513656006578039321509223503613936159072143873462875996315713 | 75 |
UVM_INFO @ 498710065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 112939991857205998673214928181133527765451696428824237727980492301001419752774 | 75 |
UVM_INFO @ 507502692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 52684126137173051073365125801293640516031478154229966602503145468064831404979 | 75 |
UVM_INFO @ 43413915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 16745972809282350251288519463278506711627125041347398886036519442867193808758 | 75 |
UVM_INFO @ 385200946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 56851766704429303780213479365877266923362873704415202946086600819267457085518 | 373 |
UVM_INFO @ 16661083615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 69147493301042363906558652714062235758852405746772629136948772185809184767839 | 234 |
UVM_INFO @ 30539806589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 52766983635506043639147235870947942354291597434320172673305477921409595309143 | 327 |
UVM_INFO @ 6721859416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 17390463592256596481301549175518884821568052036101352972275606955931019321729 | 365 |
UVM_INFO @ 37913738970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 1 test run | |||
| rv_timer_max | 35024744537993830516331264974052996547535624468388809622517188075163323949645 | 75 |
UVM_INFO @ 89550654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|