Simulation Results: sram_ctrl/main

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.85 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 2835.071us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.507us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.846us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 37.116us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.448us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 908.962us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 16.846us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 23.448us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 285.000s 96727.013us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 121.000s 5196.059us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 57.000s 7405.762us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 196.000s 12214.754us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 199.000s 101026.421us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 82.000s 14596.838us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 75.000s 53254.940us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 85.000s 91253.948us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 8.000s 1460.838us 8 8 100.00
sram_ctrl_partial_access_b2b 276.000s 7937.541us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 686.279us 0 8 0.00
sram_ctrl_throughput_w_partial_write 8.000s 9411.771us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 9488.215us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 22.000s 8836.078us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 344.534us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 681.000s 182411.606us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 27.296us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 717.556us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 717.556us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 13.507us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.846us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 23.448us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 26.165us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 13.507us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.846us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 23.448us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 26.165us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 34.000s 14665.936us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 327.897us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 211.001us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 327.897us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 211.001us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 22.000s 8836.078us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 22.000s 8836.078us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.846us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 85.000s 91253.948us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 85.000s 91253.948us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 85.000s 91253.948us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 75.000s 53254.940us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 8.000s 9467.820us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 34.000s 14665.936us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 8.000s 3718.674us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 2835.071us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 2835.071us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 85.000s 91253.948us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 327.897us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 75.000s 53254.940us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 327.897us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 327.897us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 2835.071us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 327.897us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 57.000s 5212.252us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 68622359766147268504154416667972788708227925031050832220572739486540668257389 86
UVM_INFO @ 933273895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 85227495413713360814251864161601609135048374755830560733308979458827050605858 86
UVM_INFO @ 746220565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 47353851342806823156427690857730479116684883142225710353949673411529492007645 86
UVM_INFO @ 1368335093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 25088939354530449181539434435690921400196556314722062367047183697387426293089 86
UVM_INFO @ 972528844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 22213223017211680918902739310782355765108019562469614787230794490344286463974 86
UVM_INFO @ 686278967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 68972799867622706119608095387617069851748463673681694095985535661599107177445 86
UVM_INFO @ 2540785833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 63892303264146111348187557184428492435860874027396580010780141995152305425310 86
UVM_INFO @ 659536754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 42911224212276700175583655412229182797076255713805235978452537869581408359472 86
UVM_INFO @ 660061769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 62575707575256736189732589655573741640277431787579444207163280378677861023171 86
UVM_INFO @ 2126940194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 78966389273228252535860261867372460814691092976352318471284860261129834010133 86
UVM_INFO @ 9411771012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 16677286210286541349975355744231363055934314146319040301122603667871392935003 86
UVM_INFO @ 2866320167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 90659458988914187265767835442436859519170108436620813297726052075448838829084 86
UVM_INFO @ 688664533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 39695727950766723677675717759544328956010630484841151661051423715787334679366 86
UVM_INFO @ 669873436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 34877876444340609305669033283334345635603219486707672580161696875100102845138 86
UVM_INFO @ 2738391085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 55300291920306291275954560324928438590465563491106179712949432838395543039346 86
UVM_INFO @ 2639132510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 70381246390410774250070961236250715693614860146821108830918084667587505453346 86
UVM_INFO @ 4695124494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 111745325135605528442874328137981529587276138516650959301271477857087872432393 86
UVM_INFO @ 3198845558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 1157793321702519772295669241728855469003313588117058309965955451923332938178 86
UVM_INFO @ 9488215398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 7757888729645109094848414613285327597200386985226135151800042842721571956708 86
UVM_INFO @ 691720839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 90893247572453279986643838774597591655992224442066018728157970622059686247417 86
UVM_INFO @ 8305476779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 57913570966206006168755278731056658291032346796056705234205480527432679671024 86
UVM_INFO @ 1384136810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 111907551107074265996777653448425457275101094567295531934951121480530564458085 86
UVM_INFO @ 1327413884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25095676194945811845929465631257514801921281493271727303094648153281215092315 86
UVM_INFO @ 2888192324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46564588748027820766876345179501837923851699802761893202791643835919517337177 86
UVM_INFO @ 1328165036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---