Simulation Results: uart

 
18/07/2026 02:41:01 DVSim: v1.49.0 sha: 99fb7bd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.87 %
  • code
  • 92.64 %
  • assert
  • 98.56 %
  • func
  • 99.41 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
97.23%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 13.430s 5378.843us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.880s 22.964us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.960s 15.495us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.040s 357.612us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.240s 31.805us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.460s 66.609us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.960s 15.495us 5 5 100.00
uart_csr_aliasing 1.240s 31.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 66.550s 130108.017us 10 10 100.00
parity 20 20 100.00
uart_smoke 13.430s 5378.843us 10 10 100.00
uart_tx_rx 66.550s 130108.017us 10 10 100.00
parity_error 20 20 100.00
uart_intr 64.850s 50003.213us 10 10 100.00
uart_rx_parity_err 281.090s 88915.220us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 66.550s 130108.017us 10 10 100.00
uart_intr 64.850s 50003.213us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 180.850s 90294.535us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 131.720s 100238.816us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 341.740s 116142.878us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 64.850s 50003.213us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 64.850s 50003.213us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 64.850s 50003.213us 10 10 100.00
perf 10 10 100.00
uart_perf 664.410s 21464.244us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 12.560s 9808.931us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 12.560s 9808.931us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 50.090s 30564.016us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 49.470s 42318.031us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 19.480s 6871.645us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 34.640s 6416.135us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 974.560s 173252.558us 10 10 100.00
stress_all 7 10 70.00
uart_stress_all 759.720s 292262.800us 7 10 70.00
alert_test 10 10 100.00
uart_alert_test 0.940s 121.763us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.950s 16.082us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.640s 266.059us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.640s 266.059us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.880s 22.964us 1 1 100.00
uart_csr_rw 0.960s 15.495us 5 5 100.00
uart_csr_aliasing 1.240s 31.805us 1 1 100.00
uart_same_csr_outstanding 1.120s 503.672us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.880s 22.964us 1 1 100.00
uart_csr_rw 0.960s 15.495us 5 5 100.00
uart_csr_aliasing 1.240s 31.805us 1 1 100.00
uart_same_csr_outstanding 1.120s 503.672us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.280s 129.699us 5 5 100.00
uart_tl_intg_err 1.740s 89.962us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.740s 89.962us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 16 20 80.00
uart_stress_all_with_rand_reset 84.340s 20947.332us 16 20 80.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 6 test runs
uart_noise_filter 38682274984723888897197588831407611161602228951674115416608230889202210467581 75
UVM_ERROR @ 15997407341 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 16066274128 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 16066305379 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (238 [0xee] vs 59 [0x3b]) reg name: uart_reg_block.rdata
UVM_ERROR @ 16167631538 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
uart_noise_filter 70232968119993200755771105760107975184726524802359325342468297960178538685932 75
UVM_ERROR @ 1345642552 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1393851632 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1393914788 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1442639642 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
uart_noise_filter 87229797068776117427113222705063990870145538622524599600393599284092070252913 75
UVM_ERROR @ 3723855451 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 3723875859 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3723977899 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3739885935 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 98737804808452576598114841438802984139378890028282075269619279148083774884069 75
UVM_ERROR @ 881133637 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1349785867 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 6
UVM_ERROR @ 1349833487 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1349857297 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 237 [0xed]) reg name: uart_reg_block.rdata
uart_noise_filter 110120240099781405942679190211499450011049461751628517342677976161667963022016 74
UVM_ERROR @ 851278880 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1997754176 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1997754176 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1998408030 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
uart_stress_all_with_rand_reset 14597239092960840639276058384077329775134601840973646034782227839450637671035 117
UVM_ERROR @ 896767067 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 970857902 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/986
UVM_INFO @ 1074726485 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/986
UVM_INFO @ 1098978986 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/986
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 4 test runs
uart_noise_filter 26521552268230078711495056779737749643167840119545695755210696885460509297416 75
UVM_ERROR @ 3197610295 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3197641222 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (155 [0x9b] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3197661840 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3197692767 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (155 [0x9b] vs 238 [0xee]) reg name: uart_reg_block.rdata
uart_stress_all_with_rand_reset 99067941689587107194379842279910500601177396757809812728348429855104601389526 101
UVM_ERROR @ 1047864185 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1047877884 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1047918981 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1047932680 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
uart_noise_filter 99272135428241068865807018095981672577120528937340094272733323585666332916119 75
UVM_ERROR @ 5680584967 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 5680675877 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 119 [0x77]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6023315667 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 6023406577 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all 64092532270119291175645128087349906195804078476175758339419297012497831483735 90
UVM_ERROR @ 91780705583 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 91780725991 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 91797685039 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 91797685039 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 2 test runs
uart_stress_all 79554275175244843949233253399207420536061234832035508875995581876641121047717 111
UVM_ERROR @ 191086498855 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 191086618855 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (27 [0x1b] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 191086698855 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 191086738855 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (27 [0x1b] vs 127 [0x7f]) reg name: uart_reg_block.rdata
uart_noise_filter 93808833134237235151016029121532766063424347607853286307660094719346745146767 74
UVM_ERROR @ 1212514122 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1212514122 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2308814122 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2308814122 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 1 test run
uart_stress_all 111650309389581584401199454992525407876337291153647675835411004983669519742642 99
UVM_INFO @ 171937780594 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 1/7
UVM_INFO @ 173338772194 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 2/7
UVM_INFO @ 174196955530 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 3/7
UVM_INFO @ 190376516338 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 4/7
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_stress_all_with_rand_reset 23380154659130296392670212223897178999518331045142499939917875273480593240704 137
UVM_ERROR @ 7014077789 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 7014077789 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 7152517789 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 7152517789 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR (cip_base_vseq.sv:1286) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
uart_stress_all_with_rand_reset 44030533273588840429101609845166010487726259141403212317588022528977183427271 223
UVM_ERROR @ 4457477647 ps: (cip_base_vseq.sv:1199) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4457477647 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 10/10
UVM_INFO @ 4457487059 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1