Simulation Results: adc_ctrl

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.30 %
  • code
  • 95.60 %
  • assert
  • 92.71 %
  • func
  • 13.59 %
  • line
  • 98.86 %
  • branch
  • 97.40 %
  • cond
  • 87.39 %
  • toggle
  • 99.76 %
  • FSM
  • 94.59 %
Validation stages
V1
95.65%
V2
49.72%
V2S
100.00%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 9 10 90.00
adc_ctrl_smoke 28.413s 0.000us 9 10 90.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 4.510s 1287.426us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.510s 511.268us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.570s 26666.309us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1039.423us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.600s 558.983us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.510s 511.268us 5 5 100.00
adc_ctrl_csr_aliasing 3.130s 1039.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 10 0.00
adc_ctrl_filters_polled 1.940s 387.068us 0 10 0.00
filters_polled_fixed 0 10 0.00
adc_ctrl_filters_polled_fixed 1.980s 422.208us 0 10 0.00
filters_interrupt 0 10 0.00
adc_ctrl_filters_interrupt 2.130s 462.554us 0 10 0.00
filters_interrupt_fixed 0 10 0.00
adc_ctrl_filters_interrupt_fixed 2.140s 486.039us 0 10 0.00
filters_wakeup 0 10 0.00
adc_ctrl_filters_wakeup 2.170s 507.617us 0 10 0.00
filters_wakeup_fixed 0 10 0.00
adc_ctrl_filters_wakeup_fixed 1.980s 442.109us 0 10 0.00
filters_both 0 10 0.00
adc_ctrl_filters_both 1.830s 365.700us 0 10 0.00
clock_gating 0 10 0.00
adc_ctrl_clock_gating 1.840s 385.587us 0 10 0.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 9.380s 4669.845us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 85.470s 45646.207us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 224.900s 120030.400us 10 10 100.00
stress_all 1 10 10.00
adc_ctrl_stress_all 95.040s 54794.519us 1 10 10.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.020s 428.867us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.260s 517.824us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 4.810s 577.610us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 4.810s 577.610us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 4.510s 1287.426us 1 1 100.00
adc_ctrl_csr_rw 2.510s 511.268us 5 5 100.00
adc_ctrl_csr_aliasing 3.130s 1039.423us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.670s 2277.720us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 4.510s 1287.426us 1 1 100.00
adc_ctrl_csr_rw 2.510s 511.268us 5 5 100.00
adc_ctrl_csr_aliasing 3.130s 1039.423us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.670s 2277.720us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 10.600s 8032.281us 5 5 100.00
adc_ctrl_tl_intg_err 20.530s 8048.234us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 20.530s 8048.234us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
adc_ctrl_stress_all_with_rand_reset 8.990s 3554.395us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 98 test runs
adc_ctrl_filters_polled 113585522170320628156303475275103725506090439020085363748461050545416894957348 386
UVM_INFO @ 514405570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 56577446582291571511228515183749674676771585281915719869761078622719037841246 386
UVM_INFO @ 331295139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 54888649673107588539040739334142579862094141666659120532159223609504084744013 386
UVM_INFO @ 382633020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 92559362696024108266759343816969995953965828251132665578677245400975727223922 386
UVM_INFO @ 289483718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 70242947264360665714256753791100478002518378085666092801917934283287348724973 386
UVM_INFO @ 451853739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 23643008731409990083138277538764296728261760575608393264218831287431845334293 386
UVM_INFO @ 412456281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 99878202304326431500913834161124624285957903248709475610588058573475724443327 386
UVM_INFO @ 492251893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 76802164124156287262170842105951597489862417228030968754430421112494153434833 386
UVM_INFO @ 404633662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 113866321960017075031056691473800634387050093519881198469779365427308650383114 443
UVM_INFO @ 2530907026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 27287654715432211411438413883684872874629470612072321008895377507893617511427 484
UVM_INFO @ 38200789238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 85274241356272052569295042120178988197497109584118600686951089108777095935412 386
UVM_INFO @ 431146546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 83998438108941364230250376683229488011590341365687445237219791227392050980767 386
UVM_INFO @ 422208153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 63092148061912552050057774635639810314427643239299717509020649384462599704326 386
UVM_INFO @ 384349543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 11131762961938221717635323304650853078688412137898724400093174723146424243446 386
UVM_INFO @ 417128021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 94199297910592758220931492196313934067918928414233593292571960697387977413367 386
UVM_INFO @ 334809410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 3280142366805263070982119586964016839219203960275546695578651785202197738764 386
UVM_INFO @ 499821222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 806877753311137129909107647112406800801789829260238784789400776376460254692 386
UVM_INFO @ 467499254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 68338759656038812014254867771477938449514755549054389346801653510900969950514 386
UVM_INFO @ 413339739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 53892907895918711300766669657153217892784243737369511397096599946315741493403 414
UVM_INFO @ 2589234451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 113482689377892626792566060495876361248885421958968217640797021009040646270173 387
UVM_INFO @ 966736083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 86037671709431623398592832066330426360198464457893739590034195130027063171604 386
UVM_INFO @ 381674024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 48934339290152048773520559092589357794878559374869692035710305416752304473455 386
UVM_INFO @ 485598965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 100873221603379502172506809255796748797572591534317064940003019627579257861436 386
UVM_INFO @ 438683182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 99862844213446219808183850734390647958142762208854494974518601521352190935125 386
UVM_INFO @ 481726897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 373803027040233895194542284652452053518499325731245395376333536477906581339 386
UVM_INFO @ 381396946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 95511468105445599028132069908230010602979392038869013652538266578576760531768 386
UVM_INFO @ 404300628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 62847579583634321634867846933342054285617737504787758179564689807518969926073 386
UVM_INFO @ 466401675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 52347555340182029119981141695801689699030701123921565693929473542373021475315 386
UVM_INFO @ 344246159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 96576605423931485570322370981248870319130904179964980822450581159693450753113 399
UVM_INFO @ 974403024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 7941913409902918642006642285474657386089238522288431234512862390053241211173 387
UVM_INFO @ 948823144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 38448351167527585293400808221112491834642843759116136770342558602770541289063 386
UVM_INFO @ 469123558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 72571749386199503494181257770650740271446156663211817108858401138277185326277 386
UVM_INFO @ 388770155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 432675403752491259631496458204993930613890518450434564181066548467984185556 386
UVM_INFO @ 354632104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 59887768127967643427608063654710050098802712043133238695847859611249476041107 386
UVM_INFO @ 374712359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 10106325241885728277600419765295338920977895740386495175739990176067864871757 386
UVM_INFO @ 271752348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 30271143734218187990261176226815033277034811146216345760589248695495474213117 386
UVM_INFO @ 273631151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 52332848306651432913388239259679888864223675592108586642346233230813659893257 386
UVM_INFO @ 455303709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 101687526210658733432709482795700002364586334771098946497748768090597416827039 386
UVM_INFO @ 395269206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 38708545819022554483327976994886478977861289302700212156234073052118702893021 392
UVM_INFO @ 798844828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 102314181681820365601777684710254958518787660710763692262014323178806396241916 498
UVM_INFO @ 54794518803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 32361234906503579058290293388558019749046341048576636565261409107507004399506 386
UVM_INFO @ 519839302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 41894880345040799707528275942263377175857001974219786597000505094060766296197 386
UVM_INFO @ 475391253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 70619108376243312958165989642852307809205099036801926799315419281539059042453 386
UVM_INFO @ 462554291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 104531829529837674936742994226603738735721283960848286737330863036144213201623 386
UVM_INFO @ 418459516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 11982753462957831680066152157900547909807489508281978239091946998030599846240 386
UVM_INFO @ 418207091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 78181361405919251269578207504616993032368246247473410868996275478087600526937 386
UVM_INFO @ 360009203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 83296552375304765624370961729508088833739346746373377788696892031503570035000 386
UVM_INFO @ 317398362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 56421091882717009693817174257456323830917633029288476272698798370829112595009 386
UVM_INFO @ 323218680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 90562227745039304743948152597078647901644985140799444516125007097281548855534 409
UVM_INFO @ 1231359181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 83906680823294132324573907571841283962700322723763796889508681779693775529658 387
UVM_INFO @ 798865391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 84008151825942168565456099174689932240551641120815812463446719332151743746970 386
UVM_INFO @ 475368072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 32503776576475761988015608485714070319699681486349018177066434231121098569675 386
UVM_INFO @ 454524200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 36116906641569852923484035313091190763202307198539519246162676450118810609271 386
UVM_INFO @ 381578041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 8820688645341862700175760240115843111001607669814468968546138009468547157983 386
UVM_INFO @ 308516608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 78407857416134919115866790272585347542567517609021149408588749172682523175347 386
UVM_INFO @ 372343373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 32530160563374016126756502854533657196257504351205229894303530977722363882753 386
UVM_INFO @ 315190231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 4201679316507107050918682096552967410518050224167420762429160688402471131073 386
UVM_INFO @ 449435769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 105583506977315122176016717820843880204530957268781645998582943367865465032282 386
UVM_INFO @ 365699784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 38798258020253378963916221166958371886419294176684005846403996975452673033893 392
UVM_INFO @ 712093322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 38652603010127486725618563608392783710151091427142704612222620986525868269774 387
UVM_INFO @ 663877394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 71509217268875891929874610259900402113652675463446076649810325060557924661530 386
UVM_INFO @ 387068279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 83658288330717298796661947652556672600253448122970455402593710145261351773455 386
UVM_INFO @ 402056651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 115082110769765311842061996599969360949742627643034691687108410545415172593256 386
UVM_INFO @ 532879453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 7617033323666473618663475424001508810547727769580391061014620747745204684196 386
UVM_INFO @ 486039183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 112116220882222166651696167311891618717099086222214331420209799685884277104438 386
UVM_INFO @ 395388283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 55635594379232835620397719479918358259782679325751535347574684798695202347727 386
UVM_INFO @ 451927944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 44135056488610206479085045662081994559394977241889894109477424554571104093325 386
UVM_INFO @ 385587118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 98229673081923839886039489027725744009905989406142339941422126574988204984214 386
UVM_INFO @ 354906053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 99252732235960976953532429787558267842925195197556834084370329849552094259357 405
UVM_INFO @ 4673761242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 86642347045331527440145608146182649494723649931821837718526537740549023666799 386
UVM_INFO @ 311720949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 58965448386955001420827635804498191273685640454495292320145179304995681475753 386
UVM_INFO @ 381562547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 58667561408863461725017871319148055431864271943627156310185473844907360879779 386
UVM_INFO @ 494174860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 86920164915235720791811816829907169198544838163307006256037716725225853604788 386
UVM_INFO @ 324620501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 99984668972896317611237439082242002590035879580712182312745481939520856665940 386
UVM_INFO @ 507616769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 102496231399111474338052470455493308007272168265158260619664538316595074674308 386
UVM_INFO @ 442108660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 28486822572329144975695571266537354046585823838947555871926294159390694840202 386
UVM_INFO @ 377843870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 624299166918975125511777703350966125113072105662592139876437022980340530561 386
UVM_INFO @ 398641900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 97116535704982628862904995715695564201481692020034557177143886313116682545984 451
UVM_INFO @ 29240239571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 39980354428543507617631457313321890250236280725796377269824207816950230653073 386
UVM_INFO @ 416966175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 43020877682311428287544909461103632481606285290448080431022427096886941966321 386
UVM_INFO @ 321357144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 33615293705512600179985467791419713939837348941439471000517272829934811149403 386
UVM_INFO @ 407818810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 30400896988751661946086851695929248485505749641148263039276447624318685109506 386
UVM_INFO @ 301639455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 76855488799997473581251116047044499479908678656684920460192258895112147040815 386
UVM_INFO @ 376689993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 48411175409354830688966673678044862473810610756900636218749270680980919667699 386
UVM_INFO @ 329753183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 81409162524881198866930866726749195817197244907467841410382981946118327198844 386
UVM_INFO @ 317104762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 35521278068347547879841177756165255035085358509878313144808714358089748091946 386
UVM_INFO @ 484074572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 77237796834540124891720578197434029841827310148333970268074292697662846532444 399
UVM_INFO @ 838951545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 22478318524713545220663338759523058431799703434398650614813425511827559576028 387
UVM_INFO @ 747535955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled 38047645812584865866178883735902355903304428675219602646646581530084180910014 386
UVM_INFO @ 434192095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 15204530065631118816601372354877305591723273559095275926360966095821369985787 386
UVM_INFO @ 391007438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 61981598986926841326729082021656948952616564420183570291237550392371446206344 386
UVM_INFO @ 322168644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 43333579805243776534638986674833425813653254842521627272010661623229481272991 386
UVM_INFO @ 288843602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 17277233881308385878089701477140878571293472644578310132471674385928614632123 386
UVM_INFO @ 440409683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 54788462842157218381339240711475523009345317561931060427213862755582379578294 386
UVM_INFO @ 440478884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 71187798466919119295812751342010104074755064202006943238794841285892741709925 386
UVM_INFO @ 268205325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 104329545954499998301767879818652792897372672919840038207685857472148427923467 386
UVM_INFO @ 297200230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 66384543740730371431511208428185807380398979338838861746759372863923991037048 406
UVM_INFO @ 724494311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 41027669675043606777696081394966327867452339826885526146844397767865386181846 387
UVM_INFO @ 911345484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
adc_ctrl_smoke 38655992068266363079238465468330047668751639714705669778981983403171443598754 None
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Jul 25 06:54 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255