Simulation Results: aes/masked

 
25/07/2026 02:41:09 DVSim: v1.49.0 sha: 72f4b42 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.23 %
  • code
  • 96.57 %
  • assert
  • 98.38 %
  • func
  • 96.75 %
  • block
  • 96.92 %
  • line
  • 97.78 %
  • branch
  • 92.73 %
  • toggle
  • 97.99 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
95.87%
V2S
90.82%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 229.759us 1 1 100.00
smoke 10 10 100.00
aes_smoke 19.000s 133.807us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 18.000s 67.485us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 13.000s 63.454us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 23.000s 791.927us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 27.000s 89.437us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 12.000s 70.679us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 13.000s 63.454us 5 5 100.00
aes_csr_aliasing 27.000s 89.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 69 70 98.57
aes_smoke 19.000s 133.807us 10 10 100.00
aes_config_error 53.000s 0.000us 49 50 98.00
aes_stress 19.000s 209.198us 10 10 100.00
key_length 69 70 98.57
aes_smoke 19.000s 133.807us 10 10 100.00
aes_config_error 53.000s 0.000us 49 50 98.00
aes_stress 19.000s 209.198us 10 10 100.00
back2back 35 35 100.00
aes_stress 19.000s 209.198us 10 10 100.00
aes_b2b 58.000s 1149.309us 25 25 100.00
backpressure 10 10 100.00
aes_stress 19.000s 209.198us 10 10 100.00
multi_message 93 95 97.89
aes_smoke 19.000s 133.807us 10 10 100.00
aes_config_error 53.000s 0.000us 49 50 98.00
aes_stress 19.000s 209.198us 10 10 100.00
aes_alert_reset 34.000s 102.103us 24 25 96.00
failure_test 83 85 97.65
aes_man_cfg_err 13.000s 132.131us 10 10 100.00
aes_config_error 53.000s 0.000us 49 50 98.00
aes_alert_reset 34.000s 102.103us 24 25 96.00
trigger_clear_test 10 10 100.00
aes_clear 36.000s 562.985us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 14.000s 957.622us 1 1 100.00
reset_recovery 24 25 96.00
aes_alert_reset 34.000s 102.103us 24 25 96.00
stress 10 10 100.00
aes_stress 19.000s 209.198us 10 10 100.00
sideload 20 20 100.00
aes_stress 19.000s 209.198us 10 10 100.00
aes_sideload 29.000s 168.578us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 20.000s 174.233us 10 10 100.00
stress_all 4 10 40.00
aes_stress_all 10801.000s 0.000us 4 10 40.00
alert_test 10 10 100.00
aes_alert_test 30.000s 96.236us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 19.000s 758.489us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 19.000s 758.489us 25 25 100.00
tl_d_outstanding_access 11 12 91.67
aes_csr_hw_reset 18.000s 67.485us 1 1 100.00
aes_csr_rw 13.000s 63.454us 5 5 100.00
aes_csr_aliasing 27.000s 89.437us 1 1 100.00
aes_same_csr_outstanding 24.000s 0.000us 4 5 80.00
tl_d_partial_access 11 12 91.67
aes_csr_hw_reset 18.000s 67.485us 1 1 100.00
aes_csr_rw 13.000s 63.454us 5 5 100.00
aes_csr_aliasing 27.000s 89.437us 1 1 100.00
aes_same_csr_outstanding 24.000s 0.000us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 8 10 80.00
aes_reseed 19.000s 6445.616us 8 10 80.00
fault_inject 587 660 88.94
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 20.000s 254.062us 19 20 95.00
tl_intg_err 30 30 100.00
aes_sec_cm 24.000s 272.282us 5 5 100.00
aes_tl_intg_err 24.000s 182.586us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 24.000s 182.586us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 24 25 96.00
aes_alert_reset 34.000s 102.103us 24 25 96.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
sec_cm_main_config_sparse 133 145 91.72
aes_smoke 19.000s 133.807us 10 10 100.00
aes_stress 19.000s 209.198us 10 10 100.00
aes_alert_reset 34.000s 102.103us 24 25 96.00
aes_core_fi 65.000s 10020.566us 89 100 89.00
sec_cm_gcm_config_sparse 148 160 92.50
aes_config_error 53.000s 0.000us 49 50 98.00
aes_stress 19.000s 209.198us 10 10 100.00
aes_core_fi 65.000s 10020.566us 89 100 89.00
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 54.000s 154.289us 19 20 95.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 22.000s 126.707us 10 10 100.00
aes_stress 19.000s 209.198us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 19.000s 209.198us 10 10 100.00
aes_sideload 29.000s 168.578us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 22.000s 126.707us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 22.000s 126.707us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 22.000s 126.707us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 22.000s 126.707us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 22.000s 126.707us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 19.000s 209.198us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 19.000s 209.198us 10 10 100.00
sec_cm_main_fsm_sparse 0 10 0.00
aes_fi 58.000s 3064.383us 0 10 0.00
sec_cm_main_fsm_redun 612 685 89.34
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
aes_ctr_fi 5.000s 90.030us 25 25 100.00
sec_cm_cipher_fsm_sparse 0 10 0.00
aes_fi 58.000s 3064.383us 0 10 0.00
sec_cm_cipher_fsm_redun 587 660 88.94
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
sec_cm_cipher_ctr_redun 323 350 92.29
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
sec_cm_ctr_fsm_sparse 0 10 0.00
aes_fi 58.000s 3064.383us 0 10 0.00
sec_cm_ctr_fsm_redun 289 335 86.27
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_ctr_fi 5.000s 90.030us 25 25 100.00
sec_cm_ghash_fsm_sparse 0 10 0.00
aes_fi 58.000s 3064.383us 0 10 0.00
sec_cm_ctrl_sparse 612 685 89.34
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
aes_ctr_fi 5.000s 90.030us 25 25 100.00
sec_cm_main_fsm_global_esc 24 25 96.00
aes_alert_reset 34.000s 102.103us 24 25 96.00
sec_cm_main_fsm_local_esc 612 685 89.34
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
aes_ctr_fi 5.000s 90.030us 25 25 100.00
sec_cm_cipher_fsm_local_esc 612 685 89.34
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
aes_ctr_fi 5.000s 90.030us 25 25 100.00
sec_cm_ctr_fsm_local_esc 289 335 86.27
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_ctr_fi 5.000s 90.030us 25 25 100.00
sec_cm_ghash_fsm_local_esc 0 10 0.00
aes_fi 58.000s 3064.383us 0 10 0.00
sec_cm_data_reg_local_esc 587 660 88.94
aes_fi 58.000s 3064.383us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 60.000s 10059.480us 323 350 92.29
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 45.000s 1120.285us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 24 test runs
aes_cipher_fi 103341797453808644506289292540322345104342557580556148737395691572815763374519 140
UVM_INFO @ 10015455105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 10846886822831057491726148443710675170449141514791664471931436784771344928747 141
UVM_INFO @ 10015301873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 17684440443631512692095794761808974720544566677112752649519826005413302309832 147
UVM_INFO @ 10029179337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 18614749921490213311390658832417999142003897596827467468870144444694323094725 143
UVM_INFO @ 10004387179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 1885312336530836822372607757717557230141222204226387737232541092534655322660 146
UVM_INFO @ 10004044586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15461495308359449834173006755156597065503301842260838683627162215116720384373 147
UVM_INFO @ 10005995269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 58280628214181748272292611640438649271631801428596574138946613695071346930573 148
UVM_INFO @ 10059480058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15307093476115206563591322568541488660257184963783471058719329691434399196251 153
UVM_INFO @ 10003394149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 20268860788659060509430261712414824339844961803238637127322005377265829047045 142
UVM_INFO @ 10034814336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 7217066179585521933100616901260805601021183418065883030624719679542107780461 140
UVM_INFO @ 10020844884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15561829338882966810711384868703647489651715777303298197644400309485401846195 147
UVM_INFO @ 10081764951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 115518663763629046397717709343697735130794173683461787610025305005258716398694 139
UVM_INFO @ 10014096247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 22125634654659197112502462624852683447822558015825629870745769712954382914754 144
UVM_INFO @ 10011713943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 80180582650839761519428123066961899758780796392127588139335019848992965650263 141
UVM_INFO @ 10008011986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23440555136585380931207680699999239556015640598345206325224646758007064486024 140
UVM_INFO @ 10020014419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 41361840953781296835601403918315243131109538133267113845081969397994312423995 141
UVM_INFO @ 10002688608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 16265755742514561135646312834123599212209992122793166422940464593613353011086 152
UVM_INFO @ 10056306916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96000940962137687751784626760395317193137027574629923278720142464482462560299 146
UVM_INFO @ 10008049171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 16588222448199916629146492500974830321652190005594529271940963514438023723352 146
UVM_INFO @ 10023358307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 87829938117677163465578004246749871270292407218932271586448429148668991812012 140
UVM_INFO @ 10007800170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 85446018633646863759122883438970858145844104196888369900168995881152155213302 141
UVM_INFO @ 10012772021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29837990249327125848596169509663491766228199573859209695344477100760345450573 148
UVM_INFO @ 10282399770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 59127426485917669078695915011812839473344914527459686020930348414862757082855 147
UVM_INFO @ 10004280581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 41892877463438455481124469505141070031362257296439855907982572739723286500858 143
UVM_INFO @ 10006735262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 22 test runs
aes_control_fi 61989887102240209071547029182606982105779409743704900735632259202524059210027 139
UVM_INFO @ 10028125393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102668517837848996987722918406137455302329442872446811099069283382873765888778 142
UVM_INFO @ 10019056756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61917299789289388365269918956192096720312142004368247136957508959510688493094 148
UVM_INFO @ 10059089217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12283609086171989544772982864001103079011878806459213754607772920146048191449 141
UVM_INFO @ 10067825066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 94528610657882985380113277434572911015796561325540997630492301151915161652039 143
UVM_INFO @ 10012261250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 8454032940922282514329122301444031047835427082922125762095596189378918677281 141
UVM_INFO @ 10006188339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 69205561043733877816286676889998120728434485498163798841191306145027290767014 145
UVM_INFO @ 10013583474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29632645845212349613813969137715577538864507115166516559530399499508911179812 146
UVM_INFO @ 10035893217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 24722428351255731264201265463962836293162999133640343694241776525691205640690 147
UVM_INFO @ 10061768625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 103817547172454074551458188973552718766816819424537669994562815668337864322092 152
UVM_INFO @ 10004221994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 70020285699129285243958243280886329910151422008321403736373649120314606908634 149
UVM_INFO @ 10018395147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 87600455850786314473234840903284101792923148167107090183678401771136463144033 150
UVM_INFO @ 10042565735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 46677341641233924745891554782415673272283851132099405924013460146967896440416 142
UVM_INFO @ 10035729821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 22141979678291100962746342540140635206063319747084239591769648524550753269698 140
UVM_INFO @ 10017440367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86353888964186431246144977360176579278267738089461213906354352125620076509723 146
UVM_INFO @ 10011798205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93284956924820985736884300101567648622569610016480742024146694243827847925284 150
UVM_INFO @ 10019354525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 112713371672624177190566079418576146512309115828496283626186614621402482252758 144
UVM_INFO @ 10042441221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 66137872670388679195286707095570544476296841725612249359250326420276168527651 140
UVM_INFO @ 10012355061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 28770263763226716884860659999153276663848416504919689031491091917232950263338 153
UVM_INFO @ 10007903822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 71317376132818187320067692626636394855024731999591904254388879023868132922271 147
UVM_INFO @ 10004950478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 5140797709658392170546787212355934708425111771327020557757061531131505967980 141
UVM_INFO @ 10005779739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102733895443508672688392480662082530545126130006265641545565961999923423994116 147
UVM_INFO @ 10026114666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 17 test runs
aes_stress_all 38122979510467545074788112296314391474109957943412966062407508323252311411093 None
aes_control_fi 97686473119007849626317702121287381217994378538656582789605535621064784332973 None
aes_control_fi 42537879720976384183441527872673188970947349926219702654067085146609447305954 None
aes_control_fi 1328773842506664336817668537987333064866077557401726823257467738833240651990 None
aes_control_fi 73880657078184498807412602178749387382472256794905312339789881253778432123405 None
aes_control_fi 72472922530569891710368202122746007815793800732144603512421522972967295882260 None
aes_cipher_fi 26512114920524865733311466439558326120503943612345337431570007691654555113680 None
aes_cipher_fi 73410482757412996850837066588263346778608427716395331237745410596831019945726 None
aes_control_fi 36145190316704852027149684317490092588765412936886574653519505519095317383814 None
aes_control_fi 3380386058531293201234320567986836778257240698513122878394369945269945476387 None
aes_control_fi 16995271720944526625657939452213749263926438740764016466820348124032459219660 None
aes_control_fi 74382241404581546224107255854374331320042107836188707080659803762550725362099 None
aes_control_fi 8473991819868078372138542668779065369997785188728668259942198253700946768653 None
aes_control_fi 54704635085132442747128704288561060660177431682099838450580448267384348486700 None
aes_control_fi 82029488502971240910607710419599025213387699656034093385712524507016936833069 None
aes_control_fi 1437369765225280232131851816336659408267720874197126497695280003324618280637 None
aes_control_fi 61609284643726246458706242479621016652780724979262000155859070770669494688694 None
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 11 test runs
aes_fi 85059286654932199629747309265312432521999997902428786313976849120476971356915 21379
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
aes_fi 62669896280182784129449188333022706170200556516027323978343045496562158172901 11013
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_stress_all 82183434950019093105719387208585722302566350542935816673038277735603619898203 23870
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 2
----| Seen: 1
----| Expected corrupted: 0
aes_fi 3529156782613121569374262529030251475357080916409649634243035227934125529710 11542
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 105354802275098341269415297773862469183711075167438017595044409691684827321667 14164
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
aes_fi 11933946582381016917018013035998352430114742628281005530229652891608340185870 5062
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
aes_stress_all 26045622240199301868269049376913267974114670869176905689085736134177189734056 13900
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_fi 99956910815201053420329652866051717119240620293782387294615589608698037315573 19008
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_fi 59628384317398730123408189898974936883884195285184828983050015209999929141632 4893
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 64545412146451616291885875790184875060216759651802779958633400686267774701338 240736
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 59453854714977737706928785495241407971830931104495631942309288654577428313261 9653
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 11 test runs
aes_core_fi 107620490643766230397149245027296549532513519968961429922140938543035219259877 153
UVM_INFO @ 10036926467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 91223206114582051834743832939272053574365751387757249513682830625075582136190 148
UVM_INFO @ 10008883238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 83922443773629145973147869855476626616973408576110400229666027950758119021635 138
UVM_INFO @ 10015725071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 37409804513329425695479682728474936329388181615214492754491714880570410853058 154
UVM_INFO @ 10182389452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 4838665943162209866231787286124315736534247668606944771179050206073152571115 154
UVM_INFO @ 10020286442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 7921542527832591967133053623002277800269619644096972839032058391559928882223 142
UVM_INFO @ 10019165891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 53829881705650796710093437562275666222919523803312682823366852613929164070222 153
UVM_INFO @ 10038966190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 68460016036278160579449554748212845197181504671694535614458564651829280477159 150
UVM_INFO @ 10012621563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 36909586965398224135944318188213784059612345267291827841972614018157847989597 146
UVM_INFO @ 10005783034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 3654230048054579869236120833561396517717689915531167083212057095357212986332 142
UVM_INFO @ 10020565982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 110587833090137311770025213361139530807495523648343789264311624087443276646792 147
UVM_INFO @ 10009798387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 8 test runs
aes_stress_all 106036429656727365488661107724077223156569794689827511073273474975382046179166 87509
UVM_INFO @ 2731188780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 90061306108739956216242431504372354830789194746383168517012606318854385048300 279
UVM_INFO @ 114313489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 13508176444289982583637972101603077927400877115942753740053955902440309927604 52208
UVM_INFO @ 1584159229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 88106548305130433580789272452357741036577637704634320158139843828381716102345 1223
UVM_INFO @ 79178291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 110844966301786205736620538758047313572728314295652731607785513430274529256790 48456
UVM_INFO @ 215972348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 31190699497848347639060265240669119490839780363803068080831801951034241566051 11384
UVM_INFO @ 52298205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 4350679568780241770379721642181915437660090263822388208055391552493013309741 169
UVM_INFO @ 81727075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 87333012906985101764198654366640829711393806107418518784149347850696064768965 1269
UVM_INFO @ 1120284610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 5 test runs
aes_stress_all_with_rand_reset 82776340439434542047153245988931834036553558698489758967464465355354885223119 828
UVM_INFO @ 1868568677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 48856696624201359146677444772382511215373502855311421372545511034179661400354 551
UVM_INFO @ 9725357113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 102093570818790221997393100263503677858898287979884095070902258773250887471132 493
UVM_INFO @ 1165142013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 51713355611310263399759987375416691262665794141955709228400958483725526663229 825
UVM_INFO @ 484517866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 41176908601186352842292341381457269635951675440067075946132852479759153150512 135
UVM_INFO @ 6164530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 2 test runs
aes_shadow_reg_errors_with_csr_rw 98335457384098407811538444228948511099830464649488026003599799648240316053010 106
UVM_INFO @ 16601786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_shadow_reg_errors 82183986208477352345841544140471546462256469188798408400381866668623274886590 106
UVM_INFO @ 6677804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
aes_same_csr_outstanding 13671898017588609983294630603693224826667368212702699687692290020678350021706 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Jul 25, 2026 at 06:57:43 UTC (total: 00:00:24)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
aes_config_error 115028173901529057610568980576525673246512305543352029243721771282726157466445 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Jul 25, 2026 at 06:57:57 UTC (total: 00:00:53)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
UVM_FATAL (cip_base_vseq.sv:465) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 106120155496751269558016004633035495624199242391143968217881898763983919182733 107
UVM_INFO @ 10001566199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:95) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset 1 test run
aes_fi 114527784934781842100951140793266092871861069998326442830860118702091374293382 17766
UVM_INFO @ 62417199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:87) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 12197318099430877657871367148561013247628440177609756984125032197839973788343 111
UVM_INFO @ 6135069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 34511973209916708088181327979987162809948896587682793034953872349575754336402 109
UVM_INFO @ 6461274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1113): Assertion AesModeValid has failed 1 test run
aes_alert_reset 20877998371725889357835282231831117223633917451226279201050191303178336192968 706
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 60688349 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 60688349 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 60688349 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 60688349 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid