| V1 |
|
100.00% |
| V2 |
|
89.55% |
| V2S |
|
99.02% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 60.600s | 4346.728us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.020s | 25.888us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 6.860s | 68.320us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 260.570s | 22645.862us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 85.400s | 1078.979us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 6.320s | 68.502us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 6.860s | 68.320us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 85.400s | 1078.979us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 293.280s | 6059.646us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 72.770s | 5679.426us | 50 | 50 | 100.00 | |
| entropy | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2705.090s | 259955.371us | 25 | 25 | 100.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 67.340s | 5276.409us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 60.600s | 4346.728us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 66.110s | 6625.696us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 74.660s | 5063.087us | 50 | 50 | 100.00 | |
| ping_timeout | 21 | 50 | 42.00 | |||
| alert_handler_ping_timeout | 473.750s | 14783.047us | 21 | 50 | 42.00 | |
| lpg | 96 | 100 | 96.00 | |||
| alert_handler_lpg | 3207.100s | 110062.631us | 48 | 50 | 96.00 | |
| alert_handler_lpg_stub_clk | 2705.200s | 61412.440us | 48 | 50 | 96.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 4553.270s | 373462.627us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 1 | 20 | 5.00 | |||
| alert_handler_entropy_stress | 24.640s | 2094.635us | 1 | 20 | 5.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.230s | 852.373us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.160s | 12.864us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 24.380s | 3639.631us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 24.380s | 3639.631us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.020s | 25.888us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.860s | 68.320us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 85.400s | 1078.979us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 28.690s | 732.953us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.020s | 25.888us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.860s | 68.320us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 85.400s | 1078.979us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 28.690s | 732.953us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 307.190s | 8756.656us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 307.190s | 8756.656us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 307.190s | 8756.656us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 307.190s | 8756.656us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1087.480s | 171054.551us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 85.310s | 5538.364us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 85.310s | 5538.364us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 307.190s | 8756.656us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 60.600s | 4346.728us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 60.600s | 4346.728us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 60.600s | 4346.728us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 60.600s | 4346.728us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 67.340s | 5276.409us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 48 | 50 | 96.00 | |||
| alert_handler_lpg | 3207.100s | 110062.631us | 48 | 50 | 96.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 67.340s | 5276.409us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2705.090s | 259955.371us | 25 | 25 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 25 | 25 | 100.00 | |||
| alert_handler_entropy | 2705.090s | 259955.371us | 25 | 25 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 24.290s | 893.847us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 10 | 50.00 | |||
| alert_handler_stress_all_with_rand_reset | 263.590s | 11459.873us | 5 | 10 | 50.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 24 test runs | |||
| alert_handler_ping_timeout | 14621020916048242486104091894325972378230592574210489937865501692949004402191 | 108 |
UVM_INFO @ 13981332180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 90383559575641313702274159885072436098265908973525570219592952173096153977317 | 90 |
UVM_INFO @ 9903237511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 18331277427643742041367099461238205681949261179485432560677049979056643449039 | 108 |
UVM_INFO @ 7340149242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 32689271978704289487168480057930931100664667766359088111409543352773742808096 | 84 |
UVM_INFO @ 5669224115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 86523890071546895521151969516569275064390111777528407548910576856970574366371 | 117 |
UVM_INFO @ 28397500612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 65033004677543189431358589405862373737437817935773218183000331303635649103249 | 87 |
UVM_INFO @ 3547393060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 65992071791140745352723930340444859714993839745367865026137784775911113278369 | 114 |
UVM_INFO @ 5789577299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 55680558155485115101135418654457437967524967661880360784696186340739656893709 | 96 |
UVM_INFO @ 3962063761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 113932987453594716453287110240531696554831246347843829506540598278706068350316 | 102 |
UVM_INFO @ 4169784347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 42442934325309512853316695849223764340453297578511559392488261926140063440784 | 111 |
UVM_INFO @ 5269213314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 76571382990547088467782997865083739746860844555393667783799214705699176813734 | 90 |
UVM_INFO @ 3271346120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 20816695774747770318076220768468260974466557761680731424238090925496795531410 | 87 |
UVM_INFO @ 6631336359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 25537910935552450491484478646353010310389900720623212999513598859303154594521 | 103 |
UVM_INFO @ 8237763721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 11701589852705951333429576947651935018014996593461468551039553258774349861184 | 84 |
UVM_INFO @ 2336874070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108896044128540020396850446168362822073694003250536062738618734246687593276988 | 87 |
UVM_INFO @ 6250012833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13629752093005512591177674823595445899160996451599627645578539944006613863007 | 105 |
UVM_INFO @ 3297819802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 11691578343194939411290986046806226239561913575945679652914336794729266456450 | 133 |
UVM_INFO @ 116118995705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 10035747551353797161749301601114253643056174170491320991494134365462877509312 | 137 |
UVM_INFO @ 38040795567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 69706766592779452647333575703970804675163912501218481371840944025934809148102 | 84 |
UVM_INFO @ 14207870191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101890150108389637011813000334771309855682613913958495101652038009160310361222 | 84 |
UVM_INFO @ 1091075063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 63132251063917428796390789218476803419349926697710290566416299413208282655110 | 93 |
UVM_INFO @ 9913251917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 83122513487204921976085561842927794557175009494893633452480662341699577816186 | 96 |
UVM_INFO @ 15774075312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 88275464195278235607886747876880352540046426817537149824500621607677298598552 | 96 |
UVM_INFO @ 11105278615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 14930293089047044759292099445719145761064149938014531369506497416942498796593 | 84 |
UVM_INFO @ 790387362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 19 test runs | |||
| alert_handler_entropy_stress | 38853785035347637561667669563958451566082893983796232381562486898818429680389 | 192 |
UVM_INFO @ 412126868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 48095995633506012263190946934436206353331891033423680442956493385823271574463 | 196 |
UVM_INFO @ 492959654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 93856105492112691459632124943977434048016480663164549545604034154478989219386 | 148 |
UVM_INFO @ 822955215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 94817489237426846722171736873416715933627002262347780400910009965887704965885 | 200 |
UVM_INFO @ 192705702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 32380893936611278285287171552798571218809299455574067710778295630898100266452 | 108 |
UVM_INFO @ 505457029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 55987745877439501387914415720919368092008446793972104095863613920010664403605 | 176 |
UVM_INFO @ 668530640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 99724050864397356548870507030303585253250498038417926374962153255186036325928 | 196 |
UVM_INFO @ 1829166137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 11159798553654357664992492333698412539901278545247199986579520508435445564468 | 166 |
UVM_INFO @ 2094634822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 86630860190402453976554030105355471359655857712780654963009881272951596988150 | 200 |
UVM_INFO @ 138386931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 50199149047034622408405685350714600251741880416700256384734987494964493009415 | 146 |
UVM_INFO @ 842906913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 98683922579973969593189605402939998217872239413068576438337533378542595134471 | 178 |
UVM_INFO @ 225296381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 37734978195278152263108034452185685839791039301151229469535974723768523881707 | 146 |
UVM_INFO @ 941411229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 51201362770000807700718394330365446365436082256635882233791561275006110333144 | 174 |
UVM_INFO @ 578170543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 67314444345142010071310636436430758200766666011346835245658013371505428829287 | 180 |
UVM_INFO @ 502122185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 103595419001101770359738022038322706559311699626537692643446598075700538019636 | 186 |
UVM_INFO @ 1630813778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 105034408407968270564855661079379674425404926838621984839501794181749553222606 | 198 |
UVM_INFO @ 318644875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 80636744969297188702626742363912784525304202498229059764786283068103919798263 | 182 |
UVM_INFO @ 217183919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47038455031177505233424737891470115854017109977162939552409057097741856480279 | 200 |
UVM_INFO @ 268744273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 16169546157467465722058076836208210247529391036665518451304526591985957151424 | 174 |
UVM_INFO @ 141618074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 6 test runs | |||
| alert_handler_ping_timeout | 48831249488109932793461912347504485670946400319558815861726792708994309375199 | 80 |
UVM_INFO @ 96811103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 68638797353929537146180163096934481532801413310006849002042669268466600288792 | 80 |
UVM_INFO @ 6296738350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 33004156436051235381787274511910835500594315367364028740992118078386959824101 | 80 |
UVM_INFO @ 2455499963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 42226458318064875393138736319831714920780166392305150197604365532964249536198 | 80 |
UVM_INFO @ 35554874312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 21303933350662630885947572344167154723921560996354189824568394036077841926892 | 80 |
UVM_INFO @ 841678759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 69404867216556786881590120526376748498791157158746146242811361867201341852581 | 80 |
UVM_INFO @ 3813643576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 5 test runs | |||
| alert_handler_stress_all_with_rand_reset | 61089305926142236918500364487595522903522342518374866766677850904308918487593 | 94 |
UVM_INFO @ 298801313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 55163781264981104152679654966227623707364736279888846653545290063096646116009 | 121 |
UVM_INFO @ 1482010684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| alert_handler_stress_all_with_rand_reset | 115200199599070296096550525606055547731838236479961803998154470061023278491551 | 107 |
UVM_INFO @ 5026755289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 15495474549087008678052171246286119149040361288729118164666832346063772980304 | 93 |
UVM_INFO @ 2373173751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 57628390674289287581960554755601299110146207859187813481526788726435695058493 | 135 |
UVM_INFO @ 9963250666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_stress_all | 31167553857416262371692002963208463180679402423915571565999082687032528104556 | 111 |
UVM_INFO @ 140957088282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail) | 1 test run | |||
| alert_handler_lpg_stub_clk | 104490897336978371728634146409520346232048857365022293976393075962743068918712 | 81 |
UVM_INFO @ 34501755690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* | 1 test run | |||
| alert_handler_lpg | 88444839503066644976551243858792294373211996083655204785189213492165163525188 | 80 |
UVM_INFO @ 73603439838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt | 1 test run | |||
| alert_handler_lpg_stub_clk | 1676490135430251938272985361624578871300054637724827052243370560845541128842 | 80 |
UVM_INFO @ 108122853993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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